A.9.2 Write data channel signals

Write data channel signals carry the write data from the master to the slave, and include the data bus and a byte lane strobe signal.

The following table shows the write data channel signals where y represents the master interface number.

Table A-18 Write data channel signals

Signal
Direction
Description
WIDMy[n:0]
Output
Write ID tag.
This signal is included to help connecting to AXI3 slave interfaces.
The width of this signal is the same as the corresponding AWIDMy[n:0] signal.
WDATAMy[127:0]
Output
Write data.
WSTRBMy[15:0]
Output
Write strobes.
WLASTMy
Output
Write last.
WUSERMy[n:0]
Output
User signal.
WCHECKSUMMy[n:0]
Output
An optional extension to the W payload that you can use to transmit checksum or parity information for the data.
The width of this signal is IMPLEMENTATION DEFINED.
WVALIDMy
Output
Write valid.
WREADYMy
Input
Write ready.
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