2.3 Clocking and reset

The CCI-550 uses ACLK and ARESETn signals for clock and reset, respectively.

The CCI-550 has a single main clock signal, ACLK, that it distributes to all sub blocks. Use external clock-domain-crossing bridges when masters and slaves connecting to the CCI-550 are in different clock domains.
The CCI-550 has a single reset domain with an active-LOW reset input signal, ARESETn. This is synchronized with the ACLK with a double-register on the input to the CCI-550 signal. You can replace this synchronizer with appropriate cells from your target library.

Note

When deasserting ARESETn, ensure that the following conditions are met for at least three ACLK cycles:
  • There is no activity on the slave interfaces.
  • The configuration inputs are static.
The CCI-550 supports the following power-saving features:
Internal regional clock gating
The CCI-550 automatically gates the clock to internal blocks that do not require the clock.
External architectural clock gating
The CCI-550 provides signaling to support implementation of your architectural clock gating strategy. The CCI-550 provides this support using the ARM® Q-Channel.
When the Q-Channel is in the Q_STOPPED state, you can safely disable the clock to the CCI-550. Any incoming transactions are stalled, and any changes to other inputs are not registered until the clock is reapplied. This clock gating can reduce dynamic power to zero when the system is idle.
External architectural power state control
The CCI-550 provides signaling to support implementing your architectural power state control. The CCI-550 provides this support using the ARM P-Channel.
See the Low Power Interface Specification, ARM® Q-Channel and P-Channel Interfaces for more information.

Note

The Q-Channel and P-Channel supersede the AXI low-power interface that products such as the CCI-400 use. For legacy IP, the Low Power Interface Specification, ARM® Q-Channel and P-Channel Interfaces provides information on linking to IP that contains an AXI low-power interface.
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