2.1 About the programmers
The Cortex‑A5 NEON MPE implementation of the VFPv4 floating-point architecture, with version 2 of the Common VFP subarchitecture supports the following functionality:
- All scalar operations are implemented entirely in hardware, with support
for all combinations of rounding modes, flush-to-zero, and Default NaN modes.
- Vector operations are not supported. Any attempt to execute a vector
operation results in a synchronous bounce, with the FPEXC.DEX bit set to 1.
- The Cortex‑A5
NEON MPE never generates an
asynchronous VFP exception.
In addition, it provides information on initializing the
NEON MPE ready for application code
Two access types are supported:
|RW||Read and write.
This section contains the following subsections: