2.4.5 Floating-point Exception Register

The FPEXC Register characteristics are:

Provides global enable control of the VFP extension.
Usage constraints
This register is:
Available in all configurations.
See 2.3 Register summary.
The following figure shows the FPEXC Register bit assignments.
Figure 2-5 FPEXC Register bit assignments
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The following table shows the FPEXC Register bit assignments.

Table 2-8 FPEXC Register bit assignments

EX The Cortex®‑A5 NEON MPE does not generate asynchronous VFP exceptions, therefore this bit is RAZ/WI.
NEON MPE enable bit:
b0 = NEON MPE disabled.
b1 = NEON MPE enabled.
The EN bit is cleared to 0 at reset.
[29] DEX
Defined synchronous instruction exceptional flag. The Cortex‑A5 NEON MPE sets this bit when generating a synchronous bounce because of an attempt to execute a vector operation. All other UNDEFINED Instruction exceptions clear this bit to zero.
See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for more information.
[28:0] Reserved RAZ/WI.


The Cortex‑A5 NEON MPE hardware does not support the deprecated VFP short vector feature. Attempts to execute VFP data-processing instructions when the FPSCR.LEN field is non-zero set the FPCSR.DEX bit and result in a synchronous VFP exception. You can use software to emulate the short vector feature, if required.
You can access the FPEXC Register with the following VMSR instructions:
VMRS <Rd>, FPEXC ; Read Floating-Point Status and Control Register
VMSR FPEXC, <Rt> ; Write Floating-Point Status and Control Register
Related reference
2.2 Advanced SIMD and VFP register access
2.3 Register summary
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