1.1.1 VFPv4 architecture hardware support

The Cortex‑A5 NEON MPE hardware supports single and double-precision add, subtract, multiply, divide, multiply and accumulate, fused multiply accumulate, and square root operations as described in the ARM VFPv4 architecture.

It provides conversions between 16-bit, 32-bit, and 64-bit floating-point formats and ARM integer word formats, with special operations to perform conversions in round-towards-zero mode for high-level language support.
All instructions are available in both the ARM and Thumb® instruction sets supported by the Cortex‑A5 processor family.
ARMv7 deprecates the use of VFP vector mode. The Cortex‑A5 NEON MPE hardware does not support VFP vector operations.
The Cortex‑A5 NEON MPE provides high-speed VFP operation without support code. In this manual, the term vector refers to Advanced SIMD integer, polynomial and single-precision vector operations. The Cortex‑A5 NEON MPE provides high speed VFP operation without support code. However, if an application requires VFP vector operation, then it must use support code. See the ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition for information on VFP vector operation support.

Note

This manual gives information specific to the Cortex‑A5 NEON MPE implementation of the ARM Advanced SIMD v2 and VFPv4 extensions. See the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition for full instruction set and usage details.
Non-ConfidentialPDF file icon PDF versionARM 100304_0001_00_en
Copyright © 2009, 2010, 2015 ARM. All rights reserved.