2.4.3 Media and VFP Feature Register 0

The MVFR0 characteristics are:

Together with MVFR1, describes the features that the NEON MPE provides.
Usage constraints
This register is:
Available in all configurations.
See 2.3 Register summary.
The following figure shows the MVFR0 bit assignments.
Figure 2-3 MVFR0 bit assignments
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The following table shows the MVFR0 bit assignments.

Table 2-6 MVFR0 bit assignments

Bits Name Function
[31:28] VFP rounding modes
All rounding modes supported
[27:24] Short vectors
Short vectors not supported
[23:20] Square root
Hardware square root operation supported
[19:16] Divide
Hardware divide supported
[15:12] VFP exception trapping
Software traps not supported
[11:8] Double-precision
VFPv4 double-precision supported
[7:4] Single-precision
VFPv4 single-precision supported
[3:0] A_SIMD registers
Thirty-two 64-bit registers supported
You can access the MVFR0 with the following VMSR instruction:
VMRS <Rd>, MVFR0 ; Read Media and VFP Feature Register 0
Related reference
2.2 Advanced SIMD and VFP register access
2.3 Register summary
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