2.3 Register summary

All NEON MPE system registers are 32-bit wide. Reserved register addresses are UNPREDICTABLE.

The following table shows the Cortex®‑A5 NEON MPE system registers.

Table 2-2 Cortex-A5 FPU system registers

Name Type Reset Description
FPSID RO 0x41023051 2.4.1 Floating-point System ID Register
FPSCR RW 0x00000000 2.4.2 Floating-point Status and Control Register
MVFR0 RO 0x10110222 2.4.3 Media and VFP Feature Register 0
MVFR1 RO 0x11111111 2.4.4 Media and VFP Feature Register 1
FPEXC RW 0x00000000 2.4.5 Floating-point Exception Register

Note

The FPINST and FPINST2 registers are not implemented, and any attempt to access them is UNPREDICTABLE.
The following table shows the processor modes for accessing the Cortex‑A5 NEON MPE system registers.

Table 2-3 Accessing Cortex‑A5 NEON MPE system registers

Register Privileged access User access
FPEXC.EN=0 FPEXC.EN=1 FPEXC.EN=0 FPEXC.EN=1
FPSID Permitted Permitted Not permitted Not permitted
FPSCR Not permitted Permitted Not permitted Permitted
MVFR0, MVFR1 Permitted Permitted Not permitted Not permitted
FPEXC Permitted Permitted Not permitted Not permitted
Non-ConfidentialPDF file icon PDF versionARM 100304_0001_00_en
Copyright © 2009, 2010, 2015 ARM. All rights reserved.