Arm® CoreLink™ MMU-600 System Memory Management Unit Technical Reference Manual

Revision r0p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the MMU-600
1.2 Compliance
1.2.1 Arm® architecture
1.2.2 SMMU architecture
1.2.3 AMBA® DTI protocol
1.2.4 AMBA® ACE-Lite and AMBA® AXI5 protocol
1.2.5 AMBA® APB protocol
1.3 Features
1.4 Interfaces
1.5 Configurable options
1.6 Product documentation and design flow
1.6.1 Documentation
1.6.2 Design flow
1.7 Product revisions
2 Functional description
2.1 About the functions
2.1.1 Translation Control Unit (TCU)
2.1.2 Translation Buffer Unit (TBU)
2.1.3 DTI interconnect
2.2 Interfaces
2.2.1 TCU interfaces
2.2.2 TBU interfaces
2.2.3 DTI interconnect interfaces
2.3 Operation
2.3.1 Performance Monitoring Unit
2.3.2 DTI overview
2.3.3 Reliability, Availability, and Serviceability
2.3.4 Quality of Service
2.3.5 Distributed Virtual Memory (DVM) messages
2.3.6 Error responses
2.3.7 Conversion between ACE-Lite and ARMv8 attributes
2.4 Constraints and limitations of use
2.4.1 SMMUv3 support
2.4.2 AMBA support
3 Programmers model
3.1 About the programmers model
3.2 SMMU architectural registers
3.3 MMU-600 memory map
3.4 Register summary
3.5 TCU Component and Peripheral ID Registers
3.6 TCU PMU Component and Peripheral ID Registers
3.7 TCU microarchitectural registers
3.7.1 TCU_CTRL
3.7.2 TCU_QOS
3.7.3 TCU_CFG
3.7.4 TCU_STATUS
3.7.5 TCU_SCR
3.7.6 TCU_NODE_CTRLn
3.7.7 TCU_NODE_STATUSn
3.8 TCU RAS registers
3.8.1 TCU_ERRFR
3.8.2 TCU_ERRCTLR
3.8.3 TCU_ERRSTATUS
3.8.4 TCU_ERRGEN
3.9 TBU Component and Peripheral ID Registers
3.10 TBU PMU Component and Peripheral ID Registers
3.11 TBU microarchitectural registers
3.11.1 TBU_CTRL
3.11.2 TBU_SCR
3.12 TBU RAS registers
3.12.1 TBU_ERRFR
3.12.2 TBU_ERRCTLR
3.12.3 TBU_ERRSTATUS
3.12.4 TBU_ERRGEN
A Signal descriptions
A.1 Clock and reset signals
A.2 TCU QTW/DVM interface signals
A.3 TCU programming interface signals
A.4 TCU SYSCO interface signals
A.5 TCU PMU snapshot interface signals
A.6 TCU LPI_PD interface signals
A.7 TCU LPI_CG interface signals
A.8 TCU DTI interface signals
A.9 TCU interrupt signals
A.10 TCU tie-off signals
A.11 TCU and TBU test and debug signals
A.12 TBU TBS interface signals
A.13 TBU TBM interface signals
A.14 TBU PMU snapshot interface signals
A.15 TBU LPI_PD interface signals
A.16 TBU LPI_CG interface signals
A.17 TBU DTI interface signals
A.18 TBU interrupt signals
A.19 TBU tie-off signals
A.20 DTI interconnect switch signals
A.21 DTI interconnect sizer signals
A.22 DTI interconnect register slice signals
B Software initialization examples
B.1 Initializing the SMMU
B.1.1 Allocating the Command queue
B.1.2 Allocating the Event queue
B.1.3 Configuring the Stream table
B.1.4 Initializing the Command queue
B.1.5 Initializing the Event queue
B.1.6 Invalidating TLBs and configuration caches
B.1.7 Creating a basic Context Descriptor
B.1.8 Creating a Stream Table Entry
B.2 Enabling the SMMU
C Revisions
C.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 16 December 2016 Confidential First release for r0p0
0000-01 19 May 2017 Confidential Second release for r0p0
0001-00 23 August 2017 Confidential First release for r0p1
0001-01 10 November 2017 Non-Confidential Second release for r0p1

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Some material in this document is based on IEEE 754-2008 IEEE Standard for Binary Floating-Point Arithmetic. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

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