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Home > Functional description > Operation > Conversion between ACE-Lite and ARMv8 attributes |
The SMMUv3 architecture defines attributes in terms of the ARMv8 architecture. The MMU-600 components are therefore required to perform conversion between ACE‑Lite and ARMv8 attributes.
The TBU must convert:
The TCU must convert ARMv8 attributes to ACE-Lite attributes when it outputs transactions on the QTW/DVM interface.
The memory attributes that apply to the TBS interface are contained in the AxCACHE and AxDOMAIN signals.
The following table shows the ACE‑Lite to ARMv8 attribute conversions that the TBU TBS interface performs.
Table 2-15 MMU-600 ACE-Lite to ARMv8 memory attribute conversions
AxCACHE attribute |
AxDOMAIN attribute |
ARMv8 memory attribute | ARMv8 shareability |
---|---|---|---|
Device Non‑bufferable | System | Device‑nGnRnE | Outer Shareable |
Device Bufferable | System | Device‑nGnRE | Outer Shareable |
Normal Non‑cacheable Bufferable Normal Non‑cacheable Non‑bufferable Write‑Through No Allocate Write‑Through Read‑allocate Write‑Through Write‑Allocate Write‑Through Read and Write‑Allocate |
Any |
Normal Inner Non‑cacheable Outer Non‑cacheable |
Outer Shareable |
Write‑Back No Allocate Write‑Back Read‑Allocate Write‑Back Write‑Allocate Write‑Back Read Allocate Write‑Allocate |
Non‑shareable Inner Shareable Outer Shareable |
Normal Inner Write‑Back Outer Write‑Back |
Non‑shareable Non‑shareable Outer Shareable |
The memory attributes that apply to the TBM and the QTW/DVM interfaces are contained in the AxCACHE and AxDOMAIN signals.
In addition, the TBU TBM interface can use the AxLOCK signal to indicate an Exclusive access. The QTW/DVM interface does not use the AxLOCK signal.
On the TBU TBM interface, a bit on AxUSER indicates whether the memory type before the conversion is Outer Cacheable.
The following table shows the ARMv8 to ACE‑Lite attribute conversions that the master interfaces perform.
Table 2-16 MMU-600 ARMv8 to ACE-Lite memory attribute conversions
ARMv8 memory attribute |
AxCACHE attribute |
AxDOMAIN attribute |
AxLOCK attribute |
AxUSER Outer Cacheable |
---|---|---|---|---|
Device-nGnRnE | Device Non‑bufferable. | System. | As Transaction Slave (TBS) AxLOCK value | 0 |
Device-GRE Device-nGRE Device-nGnRE |
Device Bufferable. | System. | As TBS AxLOCK value | 0 |
Normal Inner Non-cacheable Outer Non-cacheable Normal Inner Write-Through Outer Non-cacheable Normal Inner Write-Back Outer Non-cacheable |
Normal Non‑cacheable Bufferable. | System. | As TBS AxLOCK value | 0 |
Normal Inner Non-cacheable Outer Write-Through Normal Inner Write-Through Outer Write-Through Normal Inner Write-Back Outer Write-Through Normal Inner Non-cacheable Outer Write-Back Normal Inner Write-Through Outer Write-Back |
Normal Non‑cacheable Bufferable. | System. | As TBS AxLOCK value | 1 |
Normal Inner Write-Back Outer Write-Back |
Write‑Back No Allocate Write‑Back Read‑Allocate. Write‑Back Write‑Allocate. Write‑Back Read and Write‑Allocate. |
If AxBURST == FIXED, Non‑shareable. If AxBURST != FIXED, the attribute reflects the ARMv8 shareability:
|
0 | 1 |