2.2.1 TCU interfaces

The MMU-600 contains various TCU interfaces.

The following figure shows the TCU interfaces.

Figure 2-4 TCU interfaces
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TCU Queue and Table Walk/Distributed Virtual Memory interface

The Queue and Table Walk/Distributed Virtual Memory (QTW/DVM) interface is an ACE-Lite+DVM master interface.

The QTW/DVM interface issues the following transaction types:

  • ReadNoSnoop.
  • WriteNoSnoop.
  • ReadOnce.
  • WriteUnique.
  • DVM Complete.

The QTW/DVM interface uses the write address transaction ID signal awid_qtw, and the read address transaction ID signal, arid_qtw. The value of awid_qtw is always 0, and the value of arid_qtw depends on the transaction type. The following table shows the possible values of arid_qtw.

Table 2-1 Possible arid_qtw values

Transaction type

arid_qtw[n:1]

arid_qtw[0]

Translation table walk

Indicates the slot that is requesting the translation table walk

1

Command queue read

All bits = 0.

0

DVM Complete

All bits = 1.

0

To support 16-bit Virtual Machine IDentifiers (VMIDs), the interface provides DVMv8.1 support.

The interface does not issue cache maintenance operations or exclusive accesses.

TCU PROG interface

The PROG interface is an AMBA APB4 slave interface. It enables software to program the MMU-600 internal registers and read the Performance Monitoring Unit (PMU) registers and the debug registers.

This interface runs synchronously with the other TCU interfaces.

The applicable address width for this interface depends on the value of TCUCFG_NUM_TBU:

  • When TCUCFG_NUM_TBU = 14, the address width is 21 bits.
  • When TCUCFG_NUM_TBU = 62, the address width is 23 bits.

Transactions are Read-As-Zero, Writes Ignored (RAZ/WI) when any of the following apply:

  • An unimplemented register is accessed.
  • PSTRB[3:0] is not 0b1111 for write transfers.
  • PPROT[1] is not set to 0 for Secure register accesses.

See the Arm® AMBA® APB Protocol Specification for more information.

TCU LPI_PD interface

This Q‑Channel slave interface manages LPI powerdown for the TCU.

See the AMBA® Low Power Interface Specification, Arm® Q‑Channel and P‑Channel Interfaces for more information.

TCU LPI_CG interface

This Q‑Channel slave interface enables LPI clock‑gating for the TCU.

See the AMBA® Low Power Interface Specification, Arm® Q‑Channel and P‑Channel Interfaces for more information.

TCU DTI interface

The DTI interface manages communication between the TBUs and the TCU, using the DTI protocol. The DTI protocol can be conveyed over different transport layer mediums, including AXI4-Stream.

The TCU includes a slave DTI interface and each TBU includes a master DTI interface. To permit bidirectional communication, each DTI interface includes one AXI4-Stream master interface and one AXI4-Stream slave interface.

See the Arm® AMBA® Distributed Translation Interface (DTI) Protocol Specification and the Arm® AMBA® 4 AXI4-Stream Protocol Specification for more information.

TCU interrupt interfaces

This interface provides global, per-context, and performance interrupts.

TCU SYSCO interface

The MMU-600 provides a hardware system coherency interface. This interface permits the TCU to remove itself from a coherency domain in response to an LPI request.

The SYSCO interface uses the syscoreq and syscoack handshake signals to enter or exit a coherency domain.

If the sup_btm signal is tied LOW:

  • syscoreq is always driven LOW and syscoack is ignored.
  • The TCU SYSCO interface is not used and can be left unconnected.

TCU tie-off signals

The TCU tie-off signals enable you to initialize various operating parameters on exit from reset state.

At reset, the value of each tie-off signal controls the respective bits in the SMMU_IDR0 Register.

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