2.2.3 DTI interconnect interfaces

The DTI interconnect includes interfaces for each of the switch, sizer, and register slice components.

DTI interconnect switch interfaces

The DTI interconnect switch component includes dedicated interfaces.

The following figure shows the DTI interconnect switch interfaces.

Figure 2-6 DTI interconnect switch interfaces
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The following table provides more information about the switch interfaces.

Table 2-2 DTI interconnect switch interfaces

Interface

Interface type

Protocol

Description

DN_Sn

Slave

AXI4‑Stream

Slave downstream interface. One DN_Sn interface is present for each slave interface.

UP_Sn

Master

Slave upstream interface. One UP_Sn interface is present for each slave interface.

DN_M

Master

Master downstream interface.

UP_M

Slave

Master upstream interface.

Note:

The interconnect switch does not store any data, and therefore does not require a Q‑Channel clock‑gating interface.

DTI interconnect sizer interfaces

The DTI interconnect sizer component includes dedicated interfaces.

The following figure shows the DTI interconnect sizer interfaces.

Figure 2-7 DTI interconnect sizer interfaces
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The following table provides more information about the sizer interfaces.

Table 2-3 DTI interconnect sizer interfaces

Interface

Interface type

Protocol

Description

LPI_CG

Slave

Q‑Channel

Clock‑gating interface.

DN_S

Slave

AXI4‑Stream

Slave downstream interface.

UP_S

Master

Slave upstream interface.

DN_M

Master

Master downstream interface.

UP_M

Slave

Master upstream interface.

DTI interconnect register slice interfaces

The DTI interconnect register slice component includes dedicated interfaces.

The following figure shows the DTI interconnect register slice interfaces.

Figure 2-8 DTI interconnect register slice interfaces
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The following table provides more information about the register slice interfaces.

Table 2-4 DTI interconnect register slice interfaces

Interface

Interface type

Protocol

Description

LPI_CG

Slave

Q‑Channel

Clock‑gating interface.

DN_S

AXI4‑Stream

Slave downstream interface.

UP_S

Master

Slave upstream interface.

DN_M

Master downstream interface.

UP_M

Slave

Master upstream interface.

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