3.3 MMU-600 memory map

The MMU-600 memory map contains all registers.

The following table shows the MMU-600 memory map with the maximum number of implemented TBUs.

Table 3-3 MMU-600 memory map

Address range Description
0x000000 - 0x03FFFC

TCU registers.

0x040000 - 0x05FFFC

0x060000 - 0x07FFFC

0x080000 - 0x09FFFC

.

.

.

0x7C0000 - 0x7DFFFC

0x7E0000 - 0x7FFFFC

TBU0 registers.

TBU1 registers

TBU2 registers.

.

.

.

TBU60 registers.

TBU61 registers.

Note:

All TBU and TCU register addresses in this manual are described relative to the beginning of the respective address range for the component.

The following table shows the MMU-600 TCU memory map.

Table 3-4 MMU-600 TCU memory map

Address Description
0x00000 - 0x0FFFC

TCU registers, page 0, including:

  • SMMUv3 registers, page 0.
  • TCU Performance Monitor Counter Group (PMCG) registers, page 0, starting at offset 0x02000.
  • TCU implementation defined registers.
0x10000 - 0x1FFFC

TCU registers, page 1.

This address range contains the SMMUv3 registers, page 1.

0x20000 - 0x2FFFC

TCU registers, page 2.

This address range contains the TCU PMCG registers, page 1, starting at offset 0x22000.

0x30000 - 0x3FFFC

Reserved.

The following table shows the MMU-600 TBU memory map.

Table 3-5 MMU-600 TBU memory map

Address Description
0x00000 - 0x0FFFC

TBU registers, page 0, including:

  • TBU PMCG registers, page 0, starting at offset 0x02000.
  • TBU implementation defined registers.
0x10000 - 0x1FFFC

TBU registers, page 1.

This address range contains the TBU PMCG registers, page 1, starting at offset 0x12000.

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