C.1 Revisions

This appendix describes the technical changes between released issues of this book.

Table C-1 Issue 0000-00

Change

Location

Affects

First release

-

-

Table C-2 Differences between Issue 0000-00 and Issue 0000-01

Change

Location

Affects

Clarified feature list.

1.3 Features.

All revisions.
Added revised information about TCU, TBU, and DTI interconnect. 2.1 About the functions. All revisions.
Added various clarifications. 2.2 Interfaces. All revisions.
Added various clarifications. 2.3.2 Performance Monitoring Unit. All revisions.

Added new section.

SMMUv3 PMU register architectural options.

All revisions.
Added information about DTI. 2.3.1 DTI overview. All revisions.
Added various clarifications. 2.3.6 Quality of Service. All revisions.
Added new section. 2.3.11 Conversion between ACE-Lite and ARMv8 attributes. All revisions.
Added various clarifications. 2.4 Constraints and limitations of use. All revisions.
Amended address ranges. 3.3 MMU-600 memory map. All revisions.
New subsection TCU and TBU PMU identification register summary. 3.4 Register summary. All revisions.
Added new section. 3.6 TCU PMU Component and Peripheral ID Registers. All revisions.
Modified bits[2:0].

3.7.1 TCU_CTRL.

All revisions.
Amended section. 3.7.7 TCU_NODE_STATUSn. All revisions.
Added new sections.

3.8.4 TCU_ERRGEN.

All revisions.
3.10 TBU PMU Component and Peripheral ID Registers.

3.12.4 TBU_ERRGEN.

Amended sections.

A.9 TCU interrupt signals.

A.12 TBU TBS interface signals.

A.13 TBU TBM interface signals.

A.18 TBU interrupt signals.

A.19 TBU tie-off signals.

All revisions.
Added new sections. A.20 DTI interconnect switch signals. All revisions.
A.21 DTI interconnect sizer signals.
A.22 DTI interconnect register slice signals.
B.1.7 Creating a basic Context Descriptor.
B.1.8 Creating a Stream Table Entry.

Table C-3 Differences between Issue 0000-01 and Issue 0001-00

Change

Location

Affects

Added new section.

1.2.5 AMBA APB protocol.

All revisions.

Modified description of Main TLB.

2.1.2 Translation Buffer Unit.

All revisions.

Added information about sup_btm signal.

2.3.7 Distributed Virtual Memory (DVM) messages.

All revisions.

Added a note about the configurability of the ID register values.

2.4.1 SMMUv3 support.

All revisions.

Modified description of SMMU_IIDR.Revision.

2.4.1 SMMUv3 support.

r0p1.

Clarified description of CleanShared, CleanInvalid, MakeInvalid, and CleanSharedPersist transaction handling.

Transactions that can result in a translation fault.

All revisions.

Added SMMU_PMCG_IRQ_STATUS to list of unimplemented PMCG registers.

3.1 About the programmers model.

All revisions.

Modified the value and description of SMMU_PIDR2[7:4] and SMMU_PIDR3[7:4].

3.5 TCU Component and Peripheral ID Registers.

3.6 TCU PMU Component and Peripheral ID Registers.

r0p1.

Modified register description.

Modified register bits [31:16] and [7:0].

3.7.1 TCU_CTRL.

r0p1.

Added information about calculating the offset of a specific register.

3.7.6 TCU_NODE_CTRLn.

3.7.7 TCU_NODE_STATUSn.

All revisions.

Added a note to DCC and DWC bit descriptions about conditions that apply when setting the bits.

3.8.4 TCU_ERRGEN.

All revisions.

Modified the value and description of SMMU_PIDR2[7:4] and SMMU_PIDR3[7:4].

3.9 TBU Component and Peripheral ID Registers.

3.10 TBU PMU Component and Peripheral ID Registers.

r0p1.

Modified register description.

Modified register bits.

3.11.1 TBU_CTRL.

r0p1.

Added a note to DMTLB bit description about conditions that apply when setting the bit.

3.12.4 TBU_ERRGEN.

All revisions.

Table C-4 Differences between Issue 0001-00 and Issue 0001-01

Change

Location

Affects

Clarified description of translation manager.

2.1.2 Translation Buffer Unit.

All revisions.

Clarified note about DTI translation requests.

2.3.2 Performance Monitoring Unit.

All revisions.

Clarified note about configurable values.

Added note to SMMU_IIDR table entry.

2.4.1 SMMUv3 support.

All revisions.

Added note to clarify reset values of architectural registers.

Modified incorrect entries for SMMU_S_GBPA in SMMUv3 architectural registers table.

3.2 SMMU architectural registers.

All revisions.

Modified introductory description of TCU_CTRL.

3.7.1 TCU_CTRL.

r0p1.

Modified register name.

3.8.2 TCU_ERRCTLR.

3.12.2 TBU_ERRCTLR.

r0p1.

Modified section title.

Removed dftclkenable signal.

Added mbistresetn and mbistreq signals.

A.11 TCU and TBU test and debug signals.

All revisions.

Table C-5 Differences between Issue 0001-01 and Issue 0002-00

Change

Location

Affects

Modified description of configuration inputs.

1.6.2 Design flow.

All revisions.

Modified AXI5 extensions list.

Removed two notes.

TBU TBS interface.

TBU TBM interface.

All revisions.

Removed information about sec_override.

Removed note.

2.3.2 Performance Monitoring Unit. All revisions.

Clarified information about SMMU_PMCG_SMR0 event filtering.

SMMUv3 architectural performance events.

MMU-600 TCU events.

MMU-600 TBU events.

All revisions.

Changed Low_Power_Signals to Wakeup_Signals in the table. AXI5 support. All revisions.
Modified reset value of NS_INIT. 3.7.5 TCU_SCR. All revisions.
Modified register names in table. 3.10 TBU PMU Component and Peripheral ID Registers. All revisions.
Modified the value of SMMU_PMCG_CIDR1. 3.10 TBU PMU Component and Peripheral ID Registers. All revisions.
Modified description of TCU tie-off signals. A.10 TCU tie-off signals All revisions.
Modified description of TBU tie-off signals. A.19 TBU tie-off signals All revisions.
Modified value and description of SMMU_PIDR3[7:4].

3.5 TCU Component and Peripheral ID Registers.

3.9 TBU Component and Peripheral ID Registers.

r0p2.
Modified value and description of SMMU_PMCG_PIDR3[7:4].

3.6 TCU PMU Component and Peripheral ID Registers.

3.10 TBU PMU Component and Peripheral ID Registers.

r0p2.

Table C-6 Differences between Issue 0002-00 and Issue 0100-00

Change

Location

Affects

Clarified description of AMBA ACE5 compliance.

1.2.4 AMBA ACE5-Lite and AMBA® AXI5 protocol.

r1p0.
Added new features.

1.3 Features.

r1p0.
Added TBU direct indexing and MTLB partitioning information to Main TLB description.

2.1.2 Translation Buffer Unit.

r1p0.
Added information about ACE configuration.

TBU TBS interface.

TBU TBM interface.

r1p0.
Modified address width.

TBU TBM interface.

All revisions.
Added new event, CC miss.

MMU-600 TCU events.

r1p0.
Added new sections.

2.3.3 ACE protection support.

Stalling faults.

2.3.4 TBU direct indexing and MTLB partitioning.

2.3.9 TCU prefetch.

r1p0.
Added new section.

2.3.8 TCU transaction handling.

All revisions.

Fixed incorrect references to aruser_s and awuser_s. Sentence now correctly refers to aruser_m and awuser_m.

Other clarifications.

2.3.12 AXI USER bits defined by the MMU-600 TBU.

All revisions.

Added information about S1HWATTR[3:0] and S2HWATTR[3:0].

2.3.12 AXI USER bits defined by the MMU-600 TBU.

r1p0.

Added PRI field to SMMU_IDR0.

Modified value of PRIQS field in SMMU_IDR1.

Added PPS field to SMMU_IDR3.

Removed statement that said PRIQ_ABT_ERR global error cannot occur.

2.4.1 SMMUv3 support.

r1p0.
Added new sections.

Upstream ACE master restrictions.

Avoiding deadlock when using fully coherent ACE masters.

r1p0.
Modified value and description of SMMU_PIDR2[7:4] and SMMU_PIDR3[7:4].

3.5 TCU Component and Peripheral ID Registers.

3.9 TBU Component and Peripheral ID Registers.

r1p0.
Removed SMMU_PRIQ_* from list of non-implemented registers.

3.1 About the programmers model.

r1p0.

Added new registers:

  • SMMU_PRIQ_BASE.
  • SMMU_PRIQ_PROD.
  • SMMU_PRIQ_CONS.
  • SMMU_PRIQ_IRQ_CFG0.
  • SMMU_PRIQ_IRQ_CFG1.
  • SMMU_PRIQ_IRQ_CFG2.

3.2 SMMU architectural registers.

r1p0.

Added new registers:

  • SMMU_PMCG_PMAUTHSTATUS.
  • SMMU_PMCG_PMDEVARCH.
  • SMMU_PMCG_PMDEVTYPE.

3.2 SMMU architectural registers.

All revisions.
Modified value and description of SMMU_PMCG_PIDR2[7:4] and SMMU_PMCG_PIDR3[7:4].

3.6 TCU PMU Component and Peripheral ID Registers.

3.10 TBU PMU Component and Peripheral ID Registers.

r1p0.
Added new signal pri_q_irpt_ns.

A.9 TCU interrupt signals.

r1p0.

Added new signals for ACE TBU configurations.

A.12 TBU TBS interface signals.

A.13 TBU TBM interface signals.

r1p0.
Added new signal cmo_disable.

A.19 TBU tie-off signals.

r1p0.
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