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The MMU-600 is a System-level Memory Management Unit (SMMU) that translates an input address to an output address. This translation is based on address mapping and memory attribute information that is available in the MMU-600 internal registers and translation tables.
The MMU-600 implements the Arm® SMMU architecture version 3.1, SMMUv3.1, as defined by the Arm® System Memory Management Unit Architecture Specification, SMMU architecture version 3.0 and version 3.1.
An address translation from an input address to an output address is described as a stage of address translation. The MMU-600 can perform:
In addition to translating an input address to an output address, a stage of address translation also defines the memory attributes of the output address. With a two-stage translation, the stage 2 translation can modify the attributes that the stage 1 translation defines. A stage of address translation can be disabled or bypassed, and the MMU-600 can define memory attributes for disabled and bypassed stages of translation.
The MMU-600 uses inputs from the requesting master to identify a context. Configuration tables in memory tell the MMU-600 how to translate each context, such as which translation tables to use.
The MMU-600 can cache the result of a translation table lookup in a Translation Lookaside Buffer (TLB). It can also cache configuration tables in a configuration cache.
The MMU-600 contains the following key components: