The MMU-600 provides the following features:
- Compliance with the SMMUv3.1 architecture:
- Support for Stage 1 translation, Stage 2 translation, and Stage 1 followed
by stage 2 translation.
- Support for ARMv8 AArch32 and AArch64 translation table formats.
- Support for 4KB, 16KB and 64KB granule sizes in AArch64 format.
- Support for Page Request Interface (PRI), as
defined by SMMUv3. PRI is an optional PCIe ATS extension that enables
support for unpinned memory in PCIe.
- Masters can be stalled while a processor handles translation faults,
enabling software support for demand paging.
- Configuration tables in memory can support millions of active translation
- Queues in memory perform MMU-600 management, no requirement to stall a
processor when it accesses the MMU-600.
- Support for PCI Express (PCIe) integration, including Address Translation Services (ATS) and Process Address Space IDs (PASIDs).
- Support for Generic Interrupt Controller (GIC) integration,
with Message Signaled Interrupts (MSIs) supported for common
- A Performance Monitoring Unit (PMU) in each TBU and TCU that
performance to be investigated.
- Reliability, Serviceability and Availability (RAS) features for
cache corruption detection and correction.
- Support for AMBA® interfaces, including:
- ACE5-Lite TBU transaction interfaces that support cache stash transactions,
deallocating transactions, and cache maintenance.
- Option to disable cache maintenance operations on a TBU, a sideband
channel protection feature.
- An architected AXI5 extension that communicates per-transaction translation
- An ACE5-Lite + Distributed Virtual Memory (DVM)
TCU table walk interface that enables ARMv8.2 processors to perform shared
TLB invalidate operations without accessing the MMU-600 directly.
- An ACE5 Low Power extension that enables the TCU to subscribe to DVM TLB
invalidate requests on powerup and powerdown without reprogramming the DTI
DTI communication between the TCU and TBUs, enabling masters to request
translations and implement TBU functionality internally.
- Support for the AMBA
Low-Power Interface (LPI) Q-Channel so that
standard controllers can control power and clock gating.
- AXI5 WAKEUP signaling on all
interfaces, including DTI and APB interfaces.
- Access protection for ACE interfaces. ACE protection aligns with the restrictions that ACE5 defines for ACE usage of the Untranslated_Transactions extension.
- Support for flexible integration:
- A configurable number of TBUs can be placed close to the masters being
- Communication between TBU and TCU over AXI4-Stream, supported using the
supplied DTI interconnect components, or any other AXI4-Stream
- DTI interconnect components support hierarchical topologies, and control of
the tradeoff between number of wires and DTI bandwidth.
- Support for high-performance translation:
- Scalable configurable micro TLB and Main TLB
(MTLB) in the TBU can reduce the number of translation requests to the
- TBU direct indexing and MTLB partitioning enable the use of MTLB entries to be managed outside the TBU, improving real-time translation performance.
- Optimization to store all architecturally defined page and block sizes,
including contiguous page and block entries, as a single entry in the TBU
and TCU TLBs.
- Per-TBU prioritization in the TCU enables high-priority transaction streams to be translated before low-priority streams.
- TCU prefetch of translation tables, which can be enabled on a per-context basis, improving translation performance for real-time masters that access memory linearly.
- Hit-Under-Miss (HUM) support in the TBU enables transactions
with different AXI IDs to be propagated out of order, when a translation is
- TBU detection of multiple transactions that require the same translation
so that only one TBU request to the TCU is required.
- TCU detection of multiple translations that require the same table in
memory so that only one TCU memory request is required.
- Multi-level, multi-stage walk caches in the TCU reduce translation cost by
performing only part of the table walk process on a miss.
- A configurable number of concurrent translations in the TBU and TCU promotes
high translation throughput.