2.1.1 Translation Control Unit

A typical SMMUv3-based system includes a single Translation Control Unit TCU. The TCU is usually the largest block in the system, and performs several roles.

The TCU:

The following figure shows the TCU.

Figure 2-2 MMU-600 TCU
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The TCU consists of:

Walk caches
The TCU includes separate four-way set-associative walk caches to store results of translation table walks. During MMU-600 configuration, the cache line entries are split to create separate walk caches that are reserved for:
  • Stage 1 level 0 table entries.
  • Stage 1 level 1 table and block entries.
  • Stage 1 level 2 table and block entries.
  • Stage 1 level 3 table entries.
  • Stage 2 level 0 table entries.
  • Stage 2 level 1 table and block entries.
  • Stage 2 level 2 table and block entries.
  • Stage 2 level 3 table entries.
To enable and disable the walk cache for a particular stage and level of translation, use the TCU_CTRL register. If an error occurs for a cache line entry, the TCU_ERRSTATUS register identifies the affected entry.
The walk cache is useful in cases where a translation request results in a miss in other TCU caches. A subsequent hit in the walk cache requires only a single memory access to complete the translation table walk and fetch the required descriptor.
Configuration cache
The configuration caches are 4-way set-associative cache structures that store configuration information. Each entry stores the Context Descriptor (CD) and Stream Table Entry (STE) contents for a translation context.


The configuration cache does not cache the contents of intermediate configuration tables.
Translation manager
The translation manager manages translation requests that are in progress. All translation table walks and configuration table walks are hazard-checked to reduce the possibility of multiple transactions requesting duplicate walks.
Translation request buffer
The translation request buffer stores translation requests from TBUs when all translation manager slots are full. The translation request buffer supports more slots than the translation manager. When correctly configured, this buffer has enough space to store all translation requests that TBUs can issue simultaneously. This buffer therefore prevents the DTI interface from becoming blocked.
The PMU counts TCU performance-related events.
Clock and power control
The TCU has its own clock and power control, provided by the Q-Channel.
Queue manager
The queue manager manages all SMMUv3 Command queues and Event queues that are stored in memory.
QTW/DVM interface
The Queue and Table Walk (QTW)/Distributed Virtual Memory (DVM) interface is an ACE-Lite+DVM master interface.
Register file
The register file implements the SMMUv3 programmers model, as defined by the Arm® System Memory Management Unit Architecture Specification, SMMU architecture version 3.0 and version 3.1.
DTI interface
The slave DTI interface uses the DTI protocol, typically over AXI4-Stream, to enable the TCU to communicate with a master component. For the MMU-600, the master component is either a TBU or a PCIe master.
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