2.1.2 Translation Buffer Unit
A typical SMMUv3-based system includes multiple Translation Buffer Units (TBUs). Each TBU is located close to the component that it provides address translation for.
A TBU intercepts transactions and provides the required translation from a
Translation Lookaside Buffer (TLB) if possible. If a
TLB does not contain the required translation, the TBU requests translations from the
TCU and then caches the translation in one of the TLBs.
The following figure shows the TBU.
The TBU consists of:
- Master and slave interfaces
- These interfaces manage the TBS and TBM interfaces.
- Micro TLB
- The TBU compares incoming transactions with translations that are cached in
the micro TLB before looking in the Main TLB
(MTLB). The micro TLB is a fully associative TLB that provides configuration
cache and TLB functionality. You can use a tie‑off signal to
configure the cache replacement policy as either round‑robin or
Pseudo Least Recently Used (PLRU).
- Main TLB
- Each TBU includes an optional Main TLB (MTLB) that caches
translation table walk entries from:
- Stage 1 translations.
- Stage 2 translations.
- Stage 1 combined with stage 2 translations.
- The MTLB is a configurable four‑way set associative cache
structure that uses a random cache replacement policy.
- If multiple translation sizes are in use, a single transaction might require
multiple lookups. Lookups are pipelined to permit a sustained rate of one lookup
- TBU direct indexing enables the MMU-600 to manage MTLB entries externally to the TBU. This improves the predictability of TBU performance, for bus masters that have real-time performance requirements.
- Translation manager
- The translation manager manages translation requests that are in progress.
Each transaction occupies a translation slot until it is propagated downstream
through the master interface. All transactions are hazard-checked to reduce the
possibility of duplicate translation requests being sent to the TCU.
- There is no restriction on the ordering of transactions with different AXI
IDs. Transactions with different AXI IDs can be propagated downstream
- All transactions with a given AXI ID value must remain ordered. The
translation manager propagates such transactions when the translation is ready,
provided no other transaction with the same AXI ID is already waiting.
- See the Arm®
AXI and ACE Protocol Specification, AXI3, AXI4, AXI5, ACE and ACE5
for more information about AXI transaction identifiers.
- Write data buffer
The optional write data buffer enables write transactions with different
AXI IDs to progress through the TBU
out‑of‑order. It reorders the data to match
the downstream transaction order.
- The PMU counts TBU performance-related events.
- Clock and power control
- The TBU has its own clock and power control, provided by the
- DTI interface
- The master DTI interface uses the DTI protocol, typically over
AXI4‑Stream, to enable the TBU to communicate with a slave
component. For the MMU-600, the slave component is the TCU. Although you can
implement DTI over different transport protocols, the MMU-600 interfaces use
- Transaction tracker
- The transaction trackers manage outstanding read and write transactions,
permitting invalidation and synchronization to take place without stalling the