3.4 Register summary

The register summary lists all MMU-600 registers and some key characteristics.

TBU identification register summary

The following table shows the TBU identification registers in offset order from the base memory address.

Table 3-6 TBU identification register summary

Offset Name Type Description
0x00FD0 SMMU_PIDR4 RO 3.9 TBU Component and Peripheral ID Registers.
0x00FD4 SMMU_PIDR5 RO
0x00FD8 SMMU_PIDR6 RO
0x00FDC SMMU_PIDR7 RO
0x00FE0 SMMU_PIDR0 RO
0x00FE4 SMMU_PIDR1 RO
0x00FE8 SMMU_PIDR2 RO
0x00FEC SMMU_PIDR3 RO
0x00FF0 SMMU_CIDR0 RO
0x00FF4 SMMU_CIDR1 RO
0x00FF8 SMMU_CIDR2 RO
0x00FFC SMMU_CIDR3 RO

TBU RAS register summary

The following table shows the TBU Reliability, Availability, and Serviceability (RAS) registers in offset order from the base memory address.

Table 3-7 TBU RAS register summary

Offset Name Type Description
0x08E80 TBU_ERRFR RO 3.12.1 TBU_ERRFR.
0x08E88 TBU_ERRCTLR RW 3.12.2 TBU_ERRCTLR.
0x08E90 TBU_ERRSTATUS RW 3.12.3 TBU_ERRSTATUS .
0x08EC0 TBU_ERRGEN RW 3.12.4 TBU_ERRGEN.

TBU microarchitectural register summary

The following table shows the TBU microarchitectural registers in offset order from the base memory address.

Table 3-8 TBU microarchitectural register summary

Offset Name Type Description
0x08E00 TBU_CTRL RW 3.11.1 TBU_CTRL.
0x08E18 TBU_SCR RW 3.11.2 TBU_SCR.

TCU identification register summary

The following table shows the TCU identification registers in offset order from the base memory address.

Table 3-9 TCU identification register summary

Offset Name Type Description
0x00FD0 SMMU_PIDR4 RO 3.5 TCU Component and Peripheral ID Registers.
0x00FD4 SMMU_PIDR5 RO
0x00FD8 SMMU_PIDR6 RO
0x00FDC SMMU_PIDR7 RO
0x00FE0 SMMU_PIDR0 RO
0x00FE4 SMMU_PIDR1 RO
0x00FE8 SMMU_PIDR2 RO
0x00FEC SMMU_PIDR3 RO
0x00FF0 SMMU_CIDR0 RO
0x00FF4 SMMU_CIDR1 RO
0x00FF8 SMMU_CIDR2 RO
0x00FFC SMMU_CIDR3 RO

TCU and TBU PMU identification register summary

The TCU and the TBU use the same PMU identification registers. The following table shows the TCU and TBU PMU identification registers in offset order from the base memory address.

Table 3-10 TCU and TBU PMU identification register summary

Offset Name Type Description
0x02FB8 SMMU_PMCG_PMAUTHSTATUS RO

3.6 TCU PMU Component and Peripheral ID Registers.

3.10 TBU PMU Component and Peripheral ID Registers.

0x02FD0 SMMU_PMCG_PIDR4 RO
0x02FD4 SMMU_PMCG_PIDR5 RO
0x02FD8 SMMU_PMCG_PIDR6 RO
0x02FDC SMMU_PMCG_PIDR7 RO
0x02FE0 SMMU_PMCG_PIDR0 RO
0x02FE4 SMMU_PMCG_PIDR1 RO
0x02FE8 SMMU_PMCG_PIDR2 RO
0x02FEC SMMU_PMCG_PIDR3 RO
0x02FF0 SMMU_PMCG_CIDR0 RO
0x02FF4 SMMU_PMCG_CIDR1 RO
0x02FF8 SMMU_PMCG_CIDR2 RO
0x02FFC SMMU_PMCG_CIDR3 RO

TCU RAS register summary

The following table shows the TCU RAS registers in offset order from the base memory address.

Table 3-11 TCU RAS register summary

Offset Name Type Description
0x08E80 TCU_ERRFR RO 3.8.1 TCU_ERRFR.
0x08E88 TCU_ERRCTLR RW 3.8.2 TCU_ERRCTLR.
0x08E90 TCU_ERRSTATUS RW 3.8.3 TCU_ERRSTATUS.
0x08EC0 TCU_ERRGEN RW 3.8.4 TCU_ERRGEN.

TCU microarchitectural register summary

The following table shows the TCU microarchitectural registers in offset order from the base memory address.

Table 3-12 TCU microarchitectural register summary

Offset Name Type Description
0x08E00 TCU_CTRL RW 3.7.1 TCU_CTRL.
0x08E04 TCU_QOS RW 3.7.2 TCU_QOS.
0x08E08 TCU_CFG RO 3.7.3 TCU_CFG.
0x08E10 TCU_STATUS RO 3.7.4 TCU_STATUS.
0x08E18 TCU_SCR RW 3.7.5 TCU_SCR.
0x09000 - 0x093FC TCU_NODE_CTRLn RW 3.7.6 TCU_NODE_CTRLn.
0x09400 - 0x097FC TCU_NODE_STATUSn RO 3.7.7 TCU_NODE_STATUSn.
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