3.12.1 TBU_ERRFR

This is the TBU Error Feature register. Use this register to discover how the TBU handles errors.

The TBU_ERRFR characteristics are:

Usage constraints

This register is read-only. When TBU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ.

Configurations

This register exists in all TBU configurations.

Attributes
Offset

0x08E80

Type

RO

Reset

0x00000081

Width

32

The following figure shows the bit assignments.

Figure 3-14 TBU_ERRFR register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 3-30 TBU_ERRFR register bit assignments

Bits Name Function
[31:8] - Reserved
[7:6] FI The value 0b10 indicates that the fault handling interrupt is controllable.
[5:2] - Reserved
[1:0] ED The value 0b01 indicates that TBU error detection is always enabled.
Non-ConfidentialPDF file icon PDF version100310_0100_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.