3.12.2 TBU_ERRCTLR

This is the TBU Error Control register. Use this register to enable fault handling interrupts.

The TBU_ERRCTLR characteristics are:

Usage constraints

When TBU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ/WI.

Configurations

This register exists in all MMU-600 configurations. An instance of this register exists for each implemented TBU.

Attributes
Offset

0x08E88

Type

RW

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 3-15 TBU_ERRCTLR register bit assignments
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The following table shows the bit assignments.

Table 3-31 TBU_ERRCTLR register bit assignments

Bits Name Function
[31:4] - Reserved
[3] FI Set this bit to 1 to enable fault handling interrupts for the TBU.
[2:0] - Reserved
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