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This is the TBU Error Control register. Use this register to enable fault handling interrupts.
The TBU_ERRCTLR characteristics are:
When TBU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ/WI.
This register exists in all MMU-600 configurations. An instance of this register exists for each implemented TBU.
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 3-31 TBU_ERRCTLR register bit assignments
|||FI||Set this bit to 1 to enable fault handling interrupts for the TBU.|