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This is the TBU Error Record Primary Syndrome register. Use this register to find out whether different types of error have occurred on the TBU.
The TBU_ERRSTATUS characteristics are:
When TBU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ/WI. To prevent race conditions, under certain circumstances, writes to some bits in this register are ignored. Typically, these writes are ignored when a new error has not yet been observed by software.
This register exists in all MMU-600 configurations. An instance of this register exists for each implemented TBU.
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 3-32 TBU_ERRSTATUS register bit assignments
Register valid. This bit is set to 1 to indicate that at least one RAS error was recorded.
Clear this bit by writing a 1 to it. If CE is not
Overflow. This bit is set to 1 to indicate that multiple correctable errors were
recorded. That is, at least one correctable error was recorded when CE !=
Clear this bit by writing a 1 to it. A write of 0 is ignored.
|[25:24]||CE||Correctable Error. This field is set to
Error code. This field provides information about the earliest unacknowledged correctable error, as follows:
Writes to this field are ignored.