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This register disables TBU features. Do not modify the bits in this register unless directed to do so by Arm.
Its characteristics are:
There are no usage constraints.
This register exists in all TBU configurations.
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 3-28 TBU_CTRL register bit assignments
|[15:0]||AUX[15:0]||Leave each of these bits as 0.|