3.11.2 TBU_SCR

The TBU Secure Control register controls whether Non‑secure software is permitted to access the TBU registers.

Its characteristics are:

Usage constraints

This register is accessible only by Secure software. Non‑secure accesses to this register are RAZ/WI.

Configurations

This register exists in all TBU configurations.

Attributes
Offset

0x08E18

Type

RW

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 3-13 TBU_SCR register bit assignments
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The following table shows the bit assignments.

Table 3-29 TBU_SCR register bit assignments

Bits Name Function
[31:2] - Reserved.
[1] NS_RAS

Non‑secure register access to RAS registers.

0When this bit is set to 0, Non‑secure accesses to register addresses 0x08E800x08EC0 are RAZ/WI.
1When this bit is set to 1, Non‑secure access to RAS registers is permitted.
[0] NS_UARCH

Non‑secure register access to TBU_CTRL.

0When this bit is set to 0, Non‑secure accesses to TBU_CTRL are RAZ/WI.
1When this bit is set to 1, Non‑secure accesses to TBU_CTRL are permitted.
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