3.8.1 TCU_ERRFR

This is the TCU Error Feature register. Use this register to discover how the TCU handles errors.

The TCU_ERRFR characteristics are:

Usage constraints

This register is read-only. When TCU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ.

Configurations

This register exists in all TCU configurations.

Attributes
Offset

0x08E80

Type

RO

Reset

0x00000082

Width

32

The following figure shows the bit assignments.

Figure 3-8 TCU_ERRFR register bit assignments
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The following table shows the bit assignments.

Table 3-22 TCU_ERRFR register bit assignments

Bits Name Function
[31:8] - Reserved
[7:6] FI The value 0b10 indicates that the fault handling interrupt is controllable.
[5:2] - Reserved
[1:0] ED The value 0b01 indicates that TCU error detection is always enabled.
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