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Arm® CoreLink™ MMU-600 System Memory Management Unit Technical Reference ManualRevision r1p0
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3.8.2 TCU_ERRCTLR

This is the TCU Error Control register. Use this register to enable fault handling interrupts.

The TCU_ERRCTLR characteristics are:

Usage constraints

When TCU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ/WI.

Configurations

This register exists in all MMU-600 configurations.

Attributes
Offset

0x08E88
Type

RW
Reset

0x00000000
Width

32

The following figure shows the bit assignments.

Figure 3-9 TCU_ERRCTLR register bit assignments
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The following table shows the bit assignments.

Table 3-23 TCU_ERRCTLR register bit assignments

Bits Name Function
[31:4] - Reserved
[3] FI

Enable fault handling interrupts:

0An interrupt is generated on ras_irpt when a fault occurs.
1No interrupt is generated when a fault occurs.
[2:0] - Reserved
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