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Home > Programmers model > TCU RAS registers > TCU_ERRCTLR |
This is the TCU Error Control register. Use this register to enable fault handling interrupts.
The TCU_ERRCTLR characteristics are:
When TCU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ/WI.
This register exists in all MMU-600 configurations.
Offset |
|
Type |
RW |
Reset |
|
Width |
32 |
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 3-23 TCU_ERRCTLR register bit assignments
Bits | Name | Function | ||||
---|---|---|---|---|---|---|
[31:4] | - | Reserved | ||||
[3] | FI |
Enable fault handling interrupts:
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[2:0] | - | Reserved |