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This is the TCU Error Record Primary Syndrome register. Use this register to find out whether different types of error have occurred on the TCU.
The TCU_ERRSTATUS characteristics are:
When TCU_SCR.NS_RAS = 0, Non-secure accesses to this register are RAZ/WI.
To prevent race conditions, under certain circumstances, writes to some bits in this register are ignored. Typically, these writes are ignored when software has not yet observed a new error.
This register exists in all TCU configurations.
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 3-24 TCU_ERRSTATUS register bit assignments
Register valid. This bit is set to 1 to indicate that at least one RAS error was recorded.
Clear this bit by writing a 1 to it. If CE is not
Overflow. This bit is set to 1 to indicate that multiple
correctable errors were recorded. That is, at least one correctable error was
recorded when CE !=
Clear this bit by writing a 1 to it. A write of 0 is ignored.
|[25:24]||CE||Correctable Error. This field is set to
Implementation defined error code. When SERR is not set to 0, this field indicates the source of the error, as follows:
Writes to this field are ignored.
Error code. This read-only field provides information about the earliest unacknowledged correctable error, as follows: