3.7.1 TCU_CTRL

The TCU Control register disables TCU features. You can disable individual walk caches to improve performance in some systems if the hit rate of the individual walk cache is very low. Do not modify the AUX bits unless directed to do so by Arm.

The TCU_CTRL characteristics are:

Usage constraints

When TCU_SCR.NS_UARCH = 0, Non‑secure accesses to this register are RAZ/WI.

Writes to this register are possible only when both SMMU_CR0.SMMUEN = 0 and SMMU_S_CR0.SMMUEN = 0. Writes at other times are ignored.

After modifying this register, software must issue an INV_ALL operation using the SMMU_S_INIT register, before it sets SMMUEN to 1. Failure to issue an INV_ALL operation results in unpredictable behavior.

Configurations

This register exists in all TCU configurations.

Attributes
Offset

0x08E00

Type

RW

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 3-1 TCU_CTRL register bit assignments
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The following table shows the bit assignments.

Table 3-15 TCU_CTRL register bit assignments

Bits Name Function
[31:16] AUX[31:16] Leave each of these bits as 0.
[15] WCS2L3_DIS

Walk cache disable.

0Stage 2 level 3 walk cache is enabled.
1Stage 2 level 3 walk cache is disabled.
[14] WCS2L2_DIS

Walk cache disable.

0Stage 2 level 2 walk cache is enabled.
1Stage 2 level 2 walk cache is disabled.
[13] WCS2L1_DIS

Walk cache disable.

0Stage 2 level 1 walk cache is enabled.
1Stage 2 level 1 walk cache is disabled.
[12] WCS2L0_DIS

Walk cache disable.

0Stage 2 level 0 walk cache is enabled.
1Stage 2 level 0 walk cache is disabled.
[11] WCS1L3_DIS

Walk cache disable.

0Stage 1 level 3 walk cache is enabled.
1Stage 1 level 3 walk cache is disabled.
[10] WCS1L2_DIS

Walk cache disable.

0Stage 1 level 2 walk cache is enabled.
1Stage 1 level 2 walk cache is disabled.
[9] WCS1L1_DIS

Walk cache disable.

0Stage 1 level 1 walk cache is enabled.
1Stage 1 level 1 walk cache is disabled.
[8] WCS1L0_DIS

Walk cache disable.

0Stage 1 level 0 walk cache is enabled.
1Stage 1 level 0 walk cache is disabled.
[7:0] AUX[7:0] Leave each of these bits as 0.
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