2.3.12 AXI USER bits defined by the MMU-600 TBU

The TBU TBM interface AxUSER signals, aruser_m and awuser_m, have 13 bits more than the corresponding signals on the TBS interface. These extra bits are output in higher-order bits of aruser_m and awuser_m.

The following table shows the MMU-600-defined aruser_m and awuser_m bits, where w represents the AXI USER bus width that TBUCFG_AxUSER_WIDTH defines.

Table 2-17 MMU-600 defined aruser_m and awuser_m bits

Bit position

Value

[w+12]

Outer Cacheable.

[w+11:n+8]

The Stream Table Entry (STE) defines the attributes.

[w+7:n+4]

The implementation defined stage 2 hardware attributes.

[w+3:n]

The implementation defined stage 1 hardware attributes.

Bits [119:116] of the STE are implementation defined in SMMUv3. When the TCU sends a DTI translation response message to a TBU, it outputs these bits in the DTI_TBU_TRANS_RESP.CTXTATTR field. The MMU-600 TBU outputs these bits as STE-defined attributes.

The TCU DTI_TBU_TRANS_RESP response also includes S1HWATTR[3:0] and S2HWATTR[3:0] fields. These fields provide the implementation defined hardware attributes for each stage of translation. The TBU reports these fields using awuser_m and aruser_m.

The S1HWATTR and S2HWATTR fields are calculated as follows:

S1HWATTR
S1HWATTR[n] is equal to bit[n+59] of the stage 1 translation table final-level descriptor when both of the following conditions apply:
  • SMMUv3 permits the bit to have an implementation defined hardware use.
  • SMMUv3 does not permit bit[n+59] of the stage 2 translation table final-level descriptor to have an implementation defined hardware use.
Otherwise, S1HWATTR[n] = 0.
S2HWATTR
S2HWATTR[n] is equal to bit[n+59] of the stage 2 translation table final-level descriptor when SMMUv3 permits that bit to have an implementation defined hardware use. Otherwise, S2HWATTR[n] = 0.

Arm recommends that systems always use the value of S1HWATTR[n] | S2HWATTR[n], that is:

  • The value of the corresponding stage 2 final-level descriptor bit, if it is enabled for hardware use and stage 2 translation is enabled.
  • The value of the corresponding stage 1 final-level descriptor bit, if it is enabled for hardware use and stage 1 translation is enabled.
  • Otherwise, 0.
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