ARM® CoreLink™ TZC-400 TrustZone® Address Space Controller Technical Reference Manual

Revision r0p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the TZC-400
1.1.1 TZC-400 overview
1.1.2 TZC-400 example system
1.2 Compliance
1.3 Features
1.4 Interfaces
1.5 Configurable options
1.6 Test features
1.7 Product documentation, design flow, and architecture
1.8 Product revisions
2 Functional Description
2.1 TZC-400 interfaces
2.1.1 Interfaces overview
2.1.2 Clock and reset signals
2.1.3 AXI low-power interface signals
2.1.4 ACE-Lite interfaces
2.1.5 QoS Virtual Networks interface
2.1.6 APB slave interface
2.1.7 Identity input signals
2.1.8 Interrupt signal
2.1.9 Revision AND configuration signal
2.2 TZC-400 operation
2.2.1 About regions
2.2.2 Speculative accesses
2.2.3 Fast path selection
2.2.4 Gate keeper
2.2.5 Barriers
2.2.6 Lock transaction sequences
2.2.7 Exclusive accesses
2.2.8 Access latencies
2.2.9 Denied ACE-Lite transactions
2.2.10 Reset
2.3 Constraints of use
2.3.1 Changing the programmers view on an active system
2.3.2 Clock gating
3 Programmers Model
3.1 About this programmers model
3.2 Register summary
3.3 Register descriptions
3.3.1 Build configuration register
3.3.2 Action register
3.3.3 Gate keeper register
3.3.4 Speculation control register
3.3.5 Interrupt status register
3.3.6 Interrupt clear register
3.3.7 Fail address low register
3.3.8 Fail address high register
3.3.9 Fail control register
3.3.10 Fail ID register
3.3.11 Region base address low register
3.3.12 Region base address high register
3.3.13 Region top address low register
3.3.14 Region top address high register
3.3.15 Region attributes register
3.3.16 Region ID access register
3.3.17 Peripheral ID 4 register
3.3.18 Peripheral ID 5 register
3.3.19 Peripheral ID 6 register
3.3.20 Peripheral ID 7 register
3.3.21 Peripheral ID 0 register
3.3.22 Peripheral ID 1 register
3.3.23 Peripheral ID 2 register
3.3.24 Peripheral ID 3 register
3.3.25 Component ID 0 register
3.3.26 Component ID 1 register
3.3.27 Component ID 2 register
3.3.28 Component ID 3 register
A Signal Descriptions
A.1 Signal direction
A.2 Clock and reset signals
A.3 AXI low-power interface signals
A.4 ACE-Lite signals
A.5 QoS Virtual Network signals
A.5.1 AXI VN signals
A.6 APB signals
A.7 Identity signals
A.8 Interrupt signal
A.9 Configuration signals
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
A 10 May 2013 Non-Confidential First release for r0p0
B 15 July 2013 Non-Confidential First release for r0p1
C 20 February 2014 Non-Confidential Second release for r0p1
0001-02 11 September 2015 Non-Confidential Source content converted to DITA. Document number changed to 100325. No technical changes have been made to the contents of the book.

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