Arm® CoreLink™ GIC-600 Generic Interrupt Controller Technical Reference Manual

Revision r1p3


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the GIC-600
1.2 Components
1.3 Compliance
1.4 Features
1.5 Test features
1.6 Product documentation
1.7 Product revisions
2 Components and configuration
2.1 Distributor
2.1.1 Distributor AXI4-Stream interfaces
2.1.2 Distributor ACE-Lite slave interface
2.1.3 Distributor ACE-Lite master interface
2.1.4 Distributor Q-Channels
2.1.5 P-Channel
2.1.6 Distributor miscellaneous signals
2.1.7 Distributor configuration
2.2 Redistributor
2.2.1 Redistributor AXI4-Stream interface
2.2.2 Redistributor GIC Stream protocol interface
2.2.3 Redistributor Q-Channel
2.2.4 Redistributor PPI signals
2.2.5 Redistributor miscellaneous input signals
2.2.6 Redistributor configuration
2.3 ITS
2.3.1 ITS ACE-Lite slave interface
2.3.2 ITS ACE-Lite master interface
2.3.3 ITS AXI4-Stream interface
2.3.4 ITS Q-Channel
2.3.5 ITS miscellaneous signals
2.3.6 ITS configuration
2.4 MSI-64 Encapsulator
2.4.1 MSI-64 ACE-Lite interfaces
2.4.2 MSI-64 miscellaneous signals
2.4.3 MSI-64 Encapsulator configuration
2.5 SPI Collator
2.5.1 SPI Collator AXI4-Stream interface
2.5.2 SPI Collator wires
2.5.3 SPI Collator power Q-Channel
2.5.4 SPI Collator configuration
2.5.5 SPI Collator clock Q-Channel
2.6 Wake Request
2.6.1 Wake Request AXI4-Stream interface
2.6.2 Wake Request miscellaneous signals
2.6.3 Wake Request configuration
2.7 Interconnect
2.7.1 Interconnect configuration
2.8 Hierarchy
3 Operation
3.1 Interrupt types
3.1.1 SGIs
3.1.2 PPIs
3.1.3 SPIs
3.1.4 LPIs
3.1.5 Choosing between LPIs and SPIs
3.2 Interrupt groups
3.3 Physical interrupt signals (PPIs and SPIs)
3.4 Affinity routing and assignment
3.5 1 of N SPI interrupt selection
3.6 Power management
3.6.1 Redistributor power management
3.6.2 Processor core power management
3.6.3 Other power management
3.7 Getting started
3.8 Security
3.9 Backwards compatibility
3.10 Interrupt translation service (ITS)
3.10.1 ITS cache control, locking, and test
3.10.2 ITS commands and errors
3.11 LPI caching
3.12 Memory access and attributes
3.13 MSI-64
3.14 RAM
3.15 Performance Monitoring Unit
3.16 Reliability, Accessibility, and Serviceability
3.16.1 Non-secure access
3.16.2 Scrub
3.16.3 Error record classification
3.16.4 ECC error reporting and recovery
3.16.5 Error recovery and fault handling interrupts
3.16.6 Error handling records
3.16.7 Bus errors
3.17 Multichip operation
3.17.1 About multichip operation
3.17.2 Connecting the chips
3.17.3 Changing the Routing table owner
3.17.4 SPI ownership
3.17.5 Power control and P-Channel
3.17.6 Isolating a chip from the system
3.17.7 SPI operation
3.17.8 LPIs and the ITS
4 Programmers model
4.1 The GIC-600 registers
4.1.1 Register map pages
4.1.2 Discovery
4.1.3 GIC-600 register access and banking
4.2 Distributor registers (GICD/GICDA) summary
4.2.1 Distributor Control Register, GICD_CTLR
4.2.2 Interrupt Controller Type Register, GICD_TYPER
4.2.3 Distributor Implementer Identification Register, GICD_IIDR
4.2.4 Function Control Register, GICD_FCTLR
4.2.5 Secure Access Control register, GICD_SAC
4.2.6 Chip Status Register, GICD_CHIPSR
4.2.7 Default Chip Register, GICD_DCHIPR
4.2.8 Chip Registers, GICD_CHIPR<n>
4.2.9 Interrupt Class Registers, GICD_ICLARn
4.2.10 Interrupt Error Registers, GICD_IERRRn
4.2.11 Configuration ID Register, GICD_CFGID
4.2.12 Peripheral ID4 register, GICD_PIDR4
4.2.13 Peripheral ID3 register, GICD_PIDR3
4.2.14 Peripheral ID2 register, GICD_PIDR2
4.2.15 Peripheral ID1 register, GICD_PIDR1
4.2.16 Peripheral ID0 register, GICD_PIDR0
4.3 Distributor registers (GICA) for message-based SPIs summary
4.4 Redistributor registers for control and physical LPIs summary
4.4.1 Redistributor Implementation Identification Register, GICR_IIDR
4.4.2 Interrupt Controller Type Register, GICR_TYPER
4.4.3 Power Management Control Register, GICR_WAKER
4.4.4 Function Control Register, GICR_FCTLR
4.4.5 Power Register, GICR_PWRR
4.4.6 Class Register, GICR_CLASS
4.4.7 Peripheral ID2 Register, GICR_PIDR2
4.5 Redistributor registers for SGIs and PPIs summary
4.5.1 Miscellaneous Status Register, GICR_MISCSTATUSR
4.5.2 Interrupt Error Valid Register, GICR_IERRVR
4.5.3 SGI Default Register, GICR_SGIDR
4.5.4 Configuration ID0 Register, GICR_CFGID0
4.5.5 Configuration ID1 Register, GICR_CFGID1
4.6 ITS control register summary
4.6.1 ITS Implementer Identification Register, GITS_IIDR
4.6.2 Interrupt Controller Type Register, GITS_TYPER
4.6.3 Function Control Register, GITS_FCTLR
4.6.4 Operations Register, GITS_OPR
4.6.5 Operation Status Register, GITS_OPSR
4.6.6 Configuration ID Register, GITS_CFGID
4.6.7 Peripheral ID2 Register, GITS_PIDR2
4.7 ITS translation register summary
4.8 GICT register summary
4.8.1 Error Record Feature Register, GICT_ERR<n>FR
4.8.2 Error Record Control Register, GICT_ERR<n>CTLR
4.8.3 Error Record Primary Status Register, GICT_ERR<n>STATUS
4.8.4 Error Record Address Register, GICT_ERR<n>ADDR
4.8.5 Error Record Miscellaneous Register 0, GICT_ERR<n>MISC0
4.8.6 Error Record Miscellaneous Register 1, GICT_ERR<n>MISC1
4.8.7 Error Group Status Register, GICT_ERRGSR
4.8.8 Error Interrupt Configuration Registers, GICT_ERRIRQCR<n>
4.8.9 Error Record ID Register, GICT_ERRIDR
4.8.10 Peripheral ID2 Register, GICT_PIDR2
4.9 GICP register summary
4.9.1 Event Counter Registers, GICP_EVCNTRn
4.9.2 Event Type Configuration Registers, GICP_EVTYPERn
4.9.3 Shadow Value Registers, GICP_SVRn
4.9.4 Filter Registers, GICP_FRn
4.9.5 Counter Enable Set Register, GICP_CNTENSET0
4.9.6 Counter Enable Clear Register 0, GICP_CNTENCLR0
4.9.7 Interrupt Contribution Enable Set Register 0, GICP_INTENSET0
4.9.8 Interrupt Contribution Enable Clear Register 0, GICP_INTENCLR0
4.9.9 Overflow Status Clear Register 0, GICP_OVSCLR0
4.9.10 Overflow Status Set Register 0, GICP_OVSSET0
4.9.11 Counter Shadow Value Capture Register, GICP_CAPR
4.9.12 Configuration Information Register, GICP_CFGR
4.9.13 Control Register, GICP_CR
4.9.14 Interrupt Configuration Register, GICP_IRQCR
4.9.15 Peripheral ID2 Register, GICP_PIDR2
A Signal descriptions
A.1 Common control signals
A.2 Power control signals
A.3 Interrupt signals
A.4 CPU interface signals
A.5 ACE interface signals
A.6 Miscellaneous signals
A.7 Interblock signals
A.8 Interdomain signals
A.9 Interchip signals
B Implementation-defined features
B.1 Implementation-defined features reference
C Revisions
C.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 29 July 2016 Confidential First release for r0p0
0000-01 26 October 2016 Confidential Second release for r0p0
0001-00 31 March 2017 Confidential First release for r0p1
0002-00 07 June 2017 Confidential First release for r0p2
0002-01 15 June 2017 Non-Confidential Second release for r0p2
0003-00 08 January 2018 Non-Confidential First release for r0p3
0102-00 02 February 2018 Non-Confidential First release for r1p2
0103-00 27 March 2018 Non-Confidential First release for r1p3

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