4.1 The GIC-600
All the GIC-600 registers have names that are constructed of mnemonics that indicate the logical block that the register belongs to and the register function.
The following information applies to the GIC-600 registers:
- The GIC-600
implements only memory-mapped registers.
- The GIC-600 has a
single base address, except for the GITS_TRANSLATER register. The base address is
not fixed and can be different for each particular system implementation.
- The offset of each register from the base address is fixed.
- Accesses to reserved or unused address locations might result in a
bus error that is based on GICT_ERR0CTLR.UE.
- Unless otherwise stated in the accompanying text:
- Do not modify reserved register bits.
- Ignore reserved register bits on reads.
- A system reset or a Cold reset, resets all register bits to zero.
ACE-Lite slave port can be 64 bits, 128 bits, or 256 bits wide, depending on the
configuration. The Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0
defines the permitted sizes of access.
Note: The GIC-600 guarantees single-copy atomicity for doubleword accesses.
- The GIC-600
supports data only in little-endian format.
- The access types for the GIC-600 are as follows:
|RW||Read and write.
|WO||Write-only, reads return as UNKNOWN.
This section contains the following subsections: