4.2 Distributor registers (GICD/GICDA) summary

The GIC-600 Distributor functions are controlled through the Distributor registers identified with the prefix GICD. The Distributor Alias registers are identified with the prefix GICDA.

The following table lists the Distributor registers in base offset order and provides a reference to the register description that is described in either this book or the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.

Address offsets are relative to the Distributor base address defined by the system memory map.

Offsets that are not shown are Reserved and RAZ/WI. Accesses to these offsets might be reported in error record 0 as a SYN_ACE_BAD access.

Table 4-2 Distributor registers (GICD/GICDA) summary

Offset Name Type Width Reset Description Architecture defined?
0x0000 GICD_CTLR RW 32 Configuration dependent 4.2.1 Distributor Control Register, GICD_CTLR Yes
0x0004 GICD_TYPER RO 32 Configuration dependent 4.2.2 Interrupt Controller Type Register, GICD_TYPER Yes
0x0008 GICD_IIDR RO 32 Configuration dependent 4.2.3 Distributor Implementer Identification Register, GICD_IIDR Yes
0x000C-0x001C - - - - Reserved -
0x0020 GICD_FCTLR RW 32 0x0 4.2.4 Function Control Register, GICD_FCTLR a
0x0024 GICD_SAC RW 32 Tie-off dependentb 4.2.5 Secure Access Control register, GICD_SAC a
0x0028-0x003C - - - - Reserved -
0x0040 GICD_SETSPI_NSR WO 32 - Non-secure SPI Set Register Yes
0x0044 - - - - Reserved -
0x0048 GICD_CLRSPI_NSR WO 32 - Non-secure SPI Clear Register Yes
0x004C - - - - Reserved -
0x0050 GICD_SETSPI_SRcd WO 32 - Secure SPI Set Register Yes
0x0054 - - - - Reserved -
0x0058 GICD_CLRSPI_SRcd WO 32 - Secure SPI Clear Register Yes
0x005C-0x007C - - - - Reserved -
0x0080-0x00FC GICD_IGROUPRned RW 32 0x0 Interrupt Group Registers Yes
0x0100-0x017C GICD_ISENABLERne RW 32 0x0 Interrupt Set-Enable Registers Yes
0x0180-0x01FC GICD_ICENABLERne RW 32 0x0 Interrupt Clear-Enable Registers Yes
0x0200-0x027C GICD_ISPENDRne RW 32 SPI wire dependent Interrupt Set-Pending Registers Yes
0x0280-0x02FC GICD_ICPENDRne RW 32 SPI wire dependent Interrupt Clear-Pending Registers Yes
0x0300-0x037C GICD_ISACTIVERne RW 32 0x0 Interrupt Set-Active Registers Yes
0x0380-0x03FC GICD_ICACTIVERne RW 32 0x0 Interrupt Clear-Active Registers Yes
0x0400-0x07FC GICD_IPRIORITYRnf RW 32 Security dependent Interrupt Priority Registers Yes
0x0800-0x0BFC - - - - Reserved -
0x0C00-0x0CFC GICD_ICFGRn RW 32 0x0 Interrupt Configuration Registers Yes
0x0D00-0x0D7C GICD_IGRPMODRn RW 32 0x0 Interrupt Group Modifier Registers Yes
0x0D80-0x0DFC - - - - Reserved -
0x0E00-0x0EFC GICD_NSACRncg RW 32 0x0 Non-secure Access Control Registers Yes
0x0F00-0x60FC - - - - Reserved -
0x6100-0x7FD8 GICD_IROUTERnh RW 64 0x0080000000

Interrupt Routing Registers.

See the Arm® GICv3 and GICv4 Software Overview.


All SPIs are reset with Interrupt_Routing_Mode == 1. The first register is GICD_IROUTER32.
0x7FDC-0xBFFC - - - - Reserved -
0xC000 GICD_CHIPSR RW 32 P-Channel dependent 4.2.6 Chip Status Register, GICD_CHIPSR a
0xC004 GICD_DCHIPR RW 32 0x0

4.2.7 Default Chip Register, GICD_DCHIPR



RW 64 0x0

4.2.8 Chip Registers, GICD_CHIPR<n>.

0xC088-0xDFFC - - - - Reserved -


RW 32 0x0 The first register is GICD_ICLAR2. 4.2.9 Interrupt Class Registers, GICD_ICLARn a


RW 32 0x0 The first register is GICD_IERRR1. 4.2.10 Interrupt Error Registers, GICD_IERRRn a
0xE180-0xEFFC - - - - Reserved -
0xF000 GICD_CFGID RO 64 Configuration dependent 4.2.11 Configuration ID Register, GICD_CFGID a
0xF008-0xFFCC - - - - Reserved -
0xFFD0 GICD_PIDR4 RO 32 0x44 4.2.12 Peripheral ID4 register, GICD_PIDR4 No
0xFFD4 GICD_PIDR5 RO 32 0x00 Peripheral ID 5 Register No
0xFFD8 GICD_PIDR6 RO 32 0x00 Peripheral ID 6 Register No
0xFFDC GICD_PIDR7 RO 32 0x00 Peripheral ID 7 Register No
0xFFE0 GICD_PIDR0 RO 32 0x92 4.2.16 Peripheral ID0 register, GICD_PIDR0 No
0xFFE4 GICD_PIDR1 RO 32 0xB4 4.2.15 Peripheral ID1 register, GICD_PIDR1 No
0xFFE8 GICD_PIDR2 RO 32 0x3B 4.2.14 Peripheral ID2 register, GICD_PIDR2 No
0xFFEC GICD_PIDR3 RO 32 0x00 4.2.13 Peripheral ID3 register, GICD_PIDR3 No
0xFFF0 GICD_CIDR0 RO 32 0x0D Component ID 0 Register No
0xFFF4 GICD_CIDR1 RO 32 0xF0 Component ID 1 Register No
0xFFF8 GICD_CIDR2 RO 32 0x05 Component ID 2 Register No
0xFFFC GICD_CIDR3 RO 32 0xB1 Component ID 3 Register No
This section contains the following subsections:
a Microarchitecture defined.
b The reset values of GICD_SAC.GICTNS and GICD_SAC.GICPNS are controlled by the gict_allow_ns and gicp_allow_ns tie-off signals respectively.
c The existence of this register depends on the configuration of the GIC-600. If Security support is not included, then this register does not exist.
d This register is only accessible from a Secure access.
e The first one of these registers does not exist when affinity routing is enabled.
f The first eight of these registers do not exist when affinity routing is enabled.
g The first four of these registers do not exist when affinity routing is enabled.
h The first 32 of these registers do not exist when affinity routing is enabled.
Non-ConfidentialPDF file icon PDF version100336_0104_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.