4.4 Redistributor registers for control and physical LPIs summary

The functions for the GIC-600 physical LPIs are controlled through the Redistributor registers identified with the prefix GICR. In GICv3, these registers start from the base address.

For more information about LPIs, see the Arm® GICv3 and GICv4 Software Overview.

For descriptions of registers that are not specific to the GIC-600, see the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.

Table 4-21 Redistributor registers for control and physical LPIs summary

Offset Name Type Width Reset Description Architecture defined?
0x0000 GICR_CTLR RW 32 0x0 Redistributor Control Register Yes
0x0004 GICR_IIDR RO 32 Configuration dependent 4.4.1 Redistributor Implementation Identification Register, GICR_IIDR Yes
0x0008 GICR_TYPER RO 64 Configuration dependent 4.4.2 Interrupt Controller Type Register, GICR_TYPER Yes
0x0010 - - - - Reserved -
0x0014 GICR_WAKER RW 32 0x3 4.4.3 Power Management Control Register, GICR_WAKER a
0x0018-0x001C - - - - Reserved -
0x0020 GICR_FCTLR RW 32 0x0 4.4.4 Function Control Register, GICR_FCTLR a
0x0024 GICR_PWRR RW 32 Configuration dependent 4.4.5 Power Register, GICR_PWRR a
0x0028 GICR_CLASS RW 32 0x0 4.4.6 Class Register, GICR_CLASS a
0x002C-0x003C - - - - Reserved -
0x0040 GICR_SETLPIRb WO 64 - - Yes
0x0048 GICR_CLRLPIRb WO 64 - - Yes
0x0050-0x006C - - - - Reserved -
0x0070 GICR_PROPBASERc RW 64 Configuration dependent Redistributor Properties Base Address Register Yes
0x0078 GICR_PENDBASERcd RW 64 Configuration dependent Redistributor LPI Pending Table Base Address Registere Yes
0x0080-0x009C - - - - Reserved -
0x00A0 GICR_INVLPIRb WO 64 - - Yes
0x00A8-0x00AC - - - - Reserved -
0x00B0 GICR_INVALLRb WO 64 - - Yes
0x00B8-0x00BC - - - - Reserved -
0x00C0 GICR_SYNCRb RO 32 0x0 - Yes
0x00C4-0xFFCC - - - - Reserved -
0xFFD0 GICR_PIDR4 RO 32 0x44 Peripheral ID 4 Register No
0xFFD4 GICR_PIDR5 RO 32 0x00 Peripheral ID 5 Register No
0xFFD8 GICR_PIDR6 RO 32 0x00 Peripheral ID 6 Register No
0xFFDC GICR_PIDR7 RO 32 0x00 Peripheral ID 7 Register No
0xFFE0 GICR_PIDR0 RO 32 0x93 Peripheral ID 0 Register No
0xFFE4 GICR_PIDR1 RO 32 0xB4 Peripheral ID 1 Register No
0xFFE8 GICR_PIDR2 RO 32 0x3B 4.4.7 Peripheral ID2 Register, GICR_PIDR2 No
0xFFEC GICR_PIDR3 RO 32 0x00 Peripheral ID 3 Register No
0xFFF0 GICR_CIDR0 RO 32 0x0D Peripheral ID 0 Register No
0xFFF4 GICR_CIDR1 RO 32 0xF0 Peripheral ID 1 Register No
0xFFF8 GICR_CIDR2 RO 32 0x05 Peripheral ID 2 Register No
0xFFFC GICR_CIDR3 RO 32 0xB1 Peripheral ID 3 Register No
This section contains the following subsections:
a Parts of this register are architecture defined and the other parts are microarchitecture defined.
b This register is present only when Direct LPI registers are configured.
c The existence of this register depends on the configuration of the GIC-600. If ITS and LPI support is not included, this register does not exist.
d Arm recommends that if possible, you set the GICR_PENDBASER Pending Table Zero bit to one. This reduces the power and time that is taken during initialization.
e This register is only accessible from a Secure access.
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