3.1.5 Choosing between LPIs and SPIs
Message-based interrupts can be either LPIs or SPIs.
The decision to use an LPI or SPI for an interrupt can be made by software, and depends on whether there are spare SPIs and if the GIC-600 has ITS support. This can be achieved by either making the peripheral write to a different GIC-600 address, or by changing the address translation for the interrupt write in the SMMU. Changing only the SMMU is possible because the registers for Non-secure message-based interrupts, GICD_SETSPI_NSR and GITS_TRANSLATER, or GICR_SETLPIR for configurations without LPI support, are at the same address offset in different pages.
The following factors can help you to decide which interrupt type is most appropriate:
- Only the ITS provides INTID translation, therefore LPIs are preferable for peripherals that are owned by a virtual machine. This is because the hypervisor can let the virtual machine program the peripheral directly, and the ITS convert the IDs of interrupts used by the virtual machine to unique physical IDs.
- LPIs are always Group 1 Non-secure, so message-based interrupts that target Secure software must use SPIs.
- Only SPIs are able to target all cores, which means that the GIC-600 attempts to automatically balance the interrupt load to cores that are active but not handling other interrupts.
- The GIC-600 can provide a greater number of LPIs than SPIs.
- You might decide not to include LPI support in a small system where the features of the ITS are not required and there are few message-based interrupts.
- SPIs usually have a better worst-case interrupt latency than LPIs. This is because SPIs have all their settings stored internally to the GIC-600, whereas LPIs that are not cached require external memory accesses. The cache hit rate is expected to be higher for the LPIs that occur more frequently. Therefore, Arm recommends that SPIs are used for any latency-sensitive interrupts that are expected to occur infrequently.
For more information, see Arm® GICv3 and GICv4 Software Overview.