3.6.2 Processor core power management

The GIC architecture defines the programming sequence to safely power down a core that is connected to the GIC-600.

The powerdown programming sequence uses the GICR_WAKER.ProcessorSleep bit. When all cores within a cluster are powered down using the architectural sequence, you can power gate the GIC Stream interface for that cluster.

Before a core is powered down, you must set the GICR_WAKER.ProcessorSleep bit to 1. The core must then poll the GICR_WAKER.ChildrenAsleep bit to ensure that there are no outstanding transactions on the GIC Stream interface of the core.

To ensure that there are no interrupts during the powerdown of the core, in a typical powerdown sequence you must:

  1. Mask interrupts on the core.
  2. Clear the CPU interface enables.
  3. Set the interrupt bypass disable on the CPU interface.

Note:

The core powerdown sequence that you use must match the core powerdown sequence that is described in the Technical Reference Manual for your processor.

When a core is powered down and the GICR_WAKER.ProcessorSleep bit is set to 1, if the GIC-600 receives an interrupt that targets only that core, it attempts to wake the core by asserting the wake_request signal that corresponds to that core. The wake_request signal is asserted by the Wake Request block and must be connected to the system power controller.

You must not set the GICR_WAKER.ProcessorSleep bit to 1 unless the core enters a power state where the GIC-600 uses the power controller to wake the core instead of the GIC Stream interface. For example, with Cortex®-A53 and Cortex‑A57, if the core enters a low-power state that is based on the Wait For Interrupt (WFI) or Wait For Event (WFE) instructions, such as retention, you must not set the GICR_WAKER.ProcessorSleep bit to 1.

Interrupts can cause the core to leave the low-power state, entered by executing a WFI or WFE instruction, as defined in the Arm® Architecture Reference Manual ARMv8, for ARMv8‑A architecture profile. The system integrator can use the cpu_active signal to ensure that interrupts that can target multiple cores are much less likely to target cores in certain low-power states. In such a system, software has more control of the conditions under which cores leave low-power states.

Note:

Interrupts that target only one core are unaffected by cpu_active and are always sent to that core. Moreover, if the GICR_WAKER.ProcessorSleep bit for that core is set, the wake_request signal is asserted for that core.

See the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 for information about power management, and about wakeup signals and their relation to the core outputs.

Non-ConfidentialPDF file icon PDF version100336_0104_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.