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The GIC-600 can be powered up and powered down using non-architectural protocols.
When powering down the GIC-600, software must preserve the state of the GIC-600, except for any LPI pending interrupts that are preserved in pending tables, as defined in the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.
You can preserve the LPI pending bits by using an implementation-defined powerdown sequence, which ensures that the memory pointed to by each GICR_PENDBASER contains the updated pending information for the LPIs. The implementation-defined powerdown sequence must:
The powerdown described sequence ensures that all LPIs that are acknowledged by a write response to the write GITS_TRANSLATER are saved to the Pending tables. Any interrupt that arrives when the Sleep bit is set to 1 is ignored, and the ACE-Lite transaction completes in accordance with the ACE protocol.
Arm recommends that you disable any interrupt sources before setting GICR_WAKER.Sleep. However, if you require wake-on-interrupt behavior, the Write to GITS_TRANSLATER must be gated upstream at a location that enables software to reprogram and enable the GIC-600 without deadlock.
When the GICR_WAKER.Quiescent bit is set, it is safe to power down the GIC-600 without losing LPI pending bits. Software must still perform other steps such as the save and restore of SPI state. However, you must provide custom mechanisms to wake the GIC-600 if any interrupts arrive that must not be ignored.
When the GIC-600 next powers up, you can program the GICR_PENDBASER registers to point to the same memory to reload the LPI pending status. If there is no requirement to reload the pending LPIs, Arm recommends that you speed up the initialization of the GIC-600 as follows:
For more information, see Arm® GICv3 and GICv4 Software Overview.