|Home > Programmer's model > Redistributor registers for control and physical LPIs summary > Power Management Control Register, GICR_WAKER|
This register controls whether the GIC-600 can be powered down.
The GICR_WAKER characteristics are:
|Usage constraints||There are no usage constraints.|
|Configurations||Available in all GIC-600 configurations.|
|Attributes||See 4.4 Redistributor registers for control and physical LPIs summary.|
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 4-24 GICR_WAKER bit assignments
Indicates that the GIC-600 is idle and can be powered down if necessary.
Indicates that the bus between the CPU interface and this Redistributor is quiescent.
0 = This Redistributor never asserts wake_request.
1 = This Redistributor must assert a wake_request if there is a pending interrupt targeted at the connected core. See 3.6.2 Processor core power management.
Indicates the sleep state:
0 = Normal operation.
1 = The GIC-600 ensures that all the caches are consistent with external memory and that it is safe to power down. See 3.6.3 Other power management.