4.5.1 Miscellaneous Status Register, GICR_MISCSTATUSR

Use this register to test the integration of the cpu_active input signals and to debug the CPU interface enables as seen by the GIC-600.

The GICR_MISCSTATUSR characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee 4.5 Redistributor registers for SGIs and PPIs summary.

The following figure shows the bit assignments.

Figure 4-24 GICR_MISCSTATUSR bit assignments
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The following table shows the bit assignments.

Table 4-30 GICR_MISCSTATUSR bit assignments

Bits Name Function
[31] cpu_active

Returns the status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read:

0 = cpu_active input signal not active.

1 = cpu_active input signal active.

This bit is undefined when ProcessorSleep or ChildrenAsleep is set for a core, because the core is presumed to be powered down.

[30] wake_request

0 = wake_request not active.

1 = wake_request asserted.

[29:5] - Reserved.
[4] AccessType

0 = Secure access.

1 = Non-secure access.

[3] - Reserved.
[2]a EnableGrp1Secure

In systems with two Security states enabled, when GICD_CTLR.DS == 0, then:

  • For Secure reads, returns the Group 1 Secure CPU interface enable.
  • For Non-secure reads, returns zero.

In systems with only a single Security state enabled, when GICD_CTLR.DS == 1, then this bit returns zero.

[1]a EnableGrp1NSecure

In systems with two Security states enabled, when GICD_CTLR.DS == 0, then:

  • For Secure reads, this bit returns the Group 1 Non-secure CPU interface enable.
  • For Non-secure reads, when GICD_CTLR.ARE_NS == 1, this bit returns the Group 1 Non-secure CPU interface enable.
  • For Non-secure reads when GICD_CTLR.ARE_NS == 0, this bit returns zero.

In systems with only a single Security state enabled, when GICD_CTLR.DS == 1, this bit returns the Group 1 CPU interface enable.

[0]a EnableGrp0

In systems with two Security states enabled, when GICD_CTLR.DS == 0, then:

  • For Secure reads, this bit returns the Group 0 CPU interface enable.
  • For Non-secure reads when GICD_CTLR.ARE_NS == 0, this bit returns the Group 1 Non-secure CPU interface enable.
  • For Non-secure reads when GICD_CTLR.ARE_NS == 1, this bit returns zero.

In systems with only a single Security state enabled, when GICD_CTLR.DS == 1, this bit returns the Group 0 CPU interface enable.

a These bits are a copy of the CPU interface group enables for the core corresponding to this Redistributor. These copies are undefined when ProcessorSleep or ChildrenSleep is set for a core, because the core is presumed to be powered down. Upstream Write packets maintain these copies that can de-synchronize after an incorrect powerdown sequence. This register enables you to debug this scenario. For more information, see the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.
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