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The GIC-600 supports up to 32 ITS blocks in the system with a limit of 16 per chip. Each ITS is responsible for translating message-based interrupts from peripherals into LPIs.
Each ITS is compliant with the GICv3 architecture and is responsible for mapping translation requests with an EventID and DeviceID through to the physical INTID (pINTID) and Collection, a group of interrupts, and finally to the target core. The following figure shows the ITS process.
To reduce memory traffic and keep interrupt latency to a minimum, GIC-600 has three two-way set associative caches in each ITS:
In small configurations, these caches might be too small to be worth the overhead of implementing them as SRAM. If ECC protection is not required for a cache implemented as an array of flops, and to reduce RAM area, you can remove ECC from each RAM individually, see the Arm®CoreLink™ GIC‑600 Generic Interrupt Controller Configuration and Integration Manual for more information.
It is common for the DeviceID to be a non-contiguous number that is derived from the PCIe RequestorID. To ensure that this does not result in a sparse DeviceID table and wasted memory, the GIC-600 supports indirect Device tables (GITS_BASERn.Indirect = 1) where the first-level table points at subtables that can be allocated at runtime. See the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 for more details.
The GIC-600 uses memory-backed collections only, which means that before the ITS is enabled by writing to GITS_CTLR.Enabled, memory must be allocated for the Device table, the Collection table, and the ITS Command queue. Inline with the architecture, these tables must be pre-cleared to 0 by software, apart from pointers to cleared level-two Device tables, unless the tables were previously populated by the GIC-600.
The GIC-600 ITS supports all GICv3 commands as described in the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.
GITS_TYPER.PTA is 0 for all configurations, which means that all references to processor cores in ITS commands are implemented through the GICR_TYPER.ProcessorNumber field.
Command and translation errors are reported through the RAS registers. See 3.16 Reliability, Accessibility, and Serviceability.
For details on how to program and use the ITS, see the GICv3 and GICv4 Software Overview.