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The GIC-600 contains a PMU for counting key GIC events from both the Distributor and any configured ITS blocks on the same chip.
The GIC events are described in Table 4-60 EVENT field encoding.
The PMU has five counters with snapshot capability and overflow interrupt.
Secure and Non-secure interrupts are counted together and therefore Non-secure software cannot, by default, access the GICP (PMU) register space. However, Secure software can decide to allow access. This can be done by programming the GICD_SAC.GICPNS bit, or by integrating the GIC with the gicp_allow_ns tie-off set HIGH.
Each PMU counter can be programmed individually to count a range of events.
To configure a counter:
The overflow interrupt can be enabled on a per counter basis by enabling the relevant bit of GICP_INTENSET0, where bit enables GICP_EVCNTR0, bit enables GICP_EVCNTR1, and so on. Similarly, the overflow interrupt enable can be disabled by corresponding writes to GICP_INTENCLR0.
When enabled, the interrupt activates at any of these events:
The GICP_OVSSET0 and GICP_OVSCLR0 can be used for save and restore operations and for testing the correct integration of the pmu_int interrupt.
The pmu_int can be used to trigger external logic, for example, to trigger a read of the captured data.
Alternatively, by programming a valid SPI ID into the GICP_IRQCR.SPIID field, the pmu_int SPI is delivered internally in accordance with normal SPI programming.
Each PMU counter GICP_EVCNTRn has a corresponding GICP_SVRn snapshot register. On a snapshot event, all five counters are copied to their backup registers so that all consistent data is copied out over a longer period.
The snapshot events are: