3.15 Performance Monitoring Unit

The GIC-600 contains a PMU for counting key GIC events from both the Distributor and any configured ITS blocks on the same chip.

Note:

Redistributor events are not tracked by the PMU. The delivery of PPI and SGI interrupts can be counted by recording calls to the core interrupt service routine.

The GIC events are described in Table   4-60 EVENT field encoding.

The PMU has five counters with snapshot capability and overflow interrupt.

Secure and Non-secure interrupts are counted together and therefore Non-secure software cannot, by default, access the GICP (PMU) register space. However, Secure software can decide to allow access. This can be done by programming the GICD_SAC.GICPNS bit, or by integrating the GIC with the gicp_allow_ns tie-off set HIGH.

Note:

If GICD_CTLR.DS == 1, the GICP register space is accessible to all software.

Count configuration

Each PMU counter can be programmed individually to count a range of events.

To configure a counter:

  1. Program the counter GICP_EVCNTRn to a known value. This could be 0 to count events, or a higher number to trigger an overflow after a known number of events.
  2. Program the associated GICP_EVTYPERn to count the required event.
  3. Program the required filter type for the event by programming GICP_FRn.
  4. Enable the counter by programming the corresponding bit in GICP_CNTENSET0.
  5. Repeat the previous steps for all counters that are required.
  6. Enable the global count enable in GICP_CR.E.

Note:

PMU registers, other than enables, do not have resets and must be programmed before use.

Overflow interrupt

The overflow interrupt can be enabled on a per counter basis by enabling the relevant bit of GICP_INTENSET0, where bit[0] enables GICP_EVCNTR0, bit[1] enables GICP_EVCNTR1, and so on. Similarly, the overflow interrupt enable can be disabled by corresponding writes to GICP_INTENCLR0.

When enabled, the interrupt activates at any of these events:

  • A write to a GICP_OVSSET0 for any counter.
  • An overflow on any enabled counter.

The GICP_OVSSET0 and GICP_OVSCLR0 can be used for save and restore operations and for testing the correct integration of the pmu_int interrupt.

The pmu_int can be used to trigger external logic, for example, to trigger a read of the captured data.

Alternatively, by programming a valid SPI ID into the GICP_IRQCR.SPIID field, the pmu_int SPI is delivered internally in accordance with normal SPI programming.

Snapshot

Each PMU counter GICP_EVCNTRn has a corresponding GICP_SVRn snapshot register. On a snapshot event, all five counters are copied to their backup registers so that all consistent data is copied out over a longer period.

The snapshot events are:

  • A handshake on the four phase sample_req/sample_ack external handshake.
  • A write of 1 to the GICP_CAPR register CAPTURE bit.
  • An overflow of an enabled counter when GICP_EVTYPERn.OVFCAP is set.

Note:

There is only one set of snapshot registers, therefore data is replaced in multiple capture events.
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