A.1 Common control signals

The following table shows the GIC-600 common control signal set.

Table A-1 Common control signals

Signal name Type Source or destination Description
[<domain>]clk Input Clock source Clock input.
[<domain>]reset_n Input Reset source Active-LOW reset. Minimum of one cycle.
dbg_[<domain>]reset_n Input Reset source

Active-LOW reset for the PMU and error records.

Only present for domain containing the Distributor.

Test signals
dftrstdisable Input DFT control logic Reset disable. Disables the external reset input for test mode. When this signal is HIGH, it forces the internal active-LOW reset HIGH, bypassing the reset synchronizer.
dftse Input Scan enable. Disables clock gates for test mode.
dftcgen Input Clock gate enable. When this signal is HIGH, it forces all the clock gates on so that all internal clocks always run.
dftramhold Input RAM hold. When this signal is HIGH, it forces all the RAM chip selects LOW, preventing accesses to the RAMs.
MBIST controller signals
[<domain>_]mbistack Output MBIST controller

MBIST mode ready.

GIC-600 acknowledges that it is ready for MBIST testing.

[<domain>_]mbistreq Input

MBIST mode request.

Request to GIC-600 to enable MBIST testing. This signal must be tied LOW during functional operation.

[<domain>_]nmbistreset Input

Resets MBIST logic.

Resets functional logic to enable MBIST operation by an active-LOW signal. This signal must be tied HIGH during functional operation.

[<domain>_]mbistaddr[variable:0]a Input MBIST controller

Logical address.

The width is based on the RAM with the largest number of words. You must drive the most significant bits to zero when accessing RAMs with fewer address bits.

[<domain>_]mbistindata[variable:0]a Input

Data in.

Write data. Width that is based on the RAM with the largest number of data bits.

[<domain>_]mbistoutdata[variable:0]a Output

Data out.

Read data. Width that is based on the RAM with the largest number of data bits.

[<domain>_]mbistwriteen Input Write control (mbistwriteen) and read control (mbistreaden). No access occurs if both enables are LOW. It is illegal to activate both enables simultaneously.
[<domain>_]mbistreaden Input
[<domain>_]mbistarray[variable:0]a Input

Array selector.

This signal controls which RAM array is accessed. For the single RAM configuration, this port is unused.

This signal is not present on a block containing only one RAM.

[<domain>_]mbistcfg Input

MBIST ALL enable.

When enabled, allows simultaneous access to all RAM arrays for maximum array power consumption.

This signal is not present on a block containing only one RAM.

a The variable is configuration-dependent.
Non-ConfidentialPDF file icon PDF version100336_0104_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.