3.3 Physical interrupt signals (PPIs and SPIs)

The GIC-600 supports two types of physical interrupt signal.

The two types of physical interrupt signal are:

Level-sensitive
The interrupt is pending while the interrupt input is asserted. As with previous Arm GICs, PPIs are active-LOW, whereas SPIs are active-HIGH by default. However, you can change these default settings, see 3.1 Interrupt types for more information.
Edge-triggered
A rising-edge on the interrupt input causes the interrupt to become pending. The pending bit is cleared later when the interrupt is activated by the CPU interface.

To set the correct settings for the system, you must program the GICD_ICFGRn and GICR_ICFGR1 registers.

The GIC-600 provides optional synchronizers on every interrupt wire input and also return signals, to enable pulse extenders when sending edge-triggered interrupts across domain boundaries, see 2.5.2 SPI Collator wires.

For more information, see Arm® GICv3 and GICv4 Software Overview and Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.

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