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The GIC-600 uses affinity routing, a hierarchical scheme, to identify connected cores and for routing interrupts to specific cores.
The Arm architecture defines a register in a core that identifies the logical address of the core in the system. This register, which is known as the Multiprocessor Identification Register (MPIDR), has a hierarchical format. Each level of the hierarchy is known as an affinity level, with the highest affinity level specified first:
The affinity of a core is represented by four 8-bit fields using dot-decimal
notation, <Aff3>.<Aff2>.<Aff1>.<Aff0>, where Aff
n is a value for affinity level
n. An example of an identification for a specific core would be
The affinity scheme matches the format of the MPIDR_EL1 register in ARMv8-A. System designers must ensure that the ID reported by the core of the MPIDR_EL1 register matches how the core is connected to the interrupt controller.
The GIC-600 allows fully flexible allocation of MPIDR. However, it has two built-in default assignments that are based on the aff0_thread configuration parameter, see the Arm®CoreLink™ GIC‑600 Generic Interrupt Controller Configuration and Integration Manual.
The following figure shows the affinity hierarchical structure.
There can be up to 256 nodes at level 3, with each node able to host 256 child level 2 nodes. Similarly each level 2 node can host 256 level 1 nodes. However, level 1 nodes can only host 16 child level 0 nodes.
For more information about affinity routing, see the Arm® GICv3 and GICv4 Software Overview, and the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.