Non-ConfidentialPDF file icon PDF version100336_0104_00_en
Arm® CoreLink™ GIC-600 Generic Interrupt Controller Technical Reference ManualRevision r1p4
Home > Operation > Memory access and attributes

3.12 Memory access and attributes

The LPI and ITS transactions are located in memory tables whose locations are defined in registers that specify their base address, size, and access attributes.

Arm recommends that all tables are placed in Normal memory. All ITS tables are private, and after allocation, are accessed only by the GIC. However, the LPI Property table and ITS Command queue are written to by cores, and read by the GIC.

The following table shows the a<x>cache and a<x>domain mappings for the memory transactions that the GIC generates.

Table 3-4 Memory access registers

Access type Register Mapping control bita
LPI Property table GICR_PROPBASER GICD_FCTLR.DCC
LPI Pending table GICR_PENDBASER
ITS Device table GITS_BASER0 GITS_FCTLR.DCC
ITS Translation table GITS_BASER0
ITS Collection table GITS_BASER1
ITS Command queue GITS_CBASER

The main cacheability value is derived from the *BASER*.OuterCache field, unless it is zero, in which case the cacheability value is a value that is shown in the following table.

Table 3-5 Cacheability values

Main cacheability value (*BASER*.OuterCache field) Other cacheability value (*BASER*.InnerCache field) arcache awcache arcache (DCC = 1) awcache (DCC = 1)
0b000, Device-nGnRnE - 0b0010 0b0010 0b0010 0b0010
0b001, Normal Non-cacheable Match 0b0011 0b0011 0b0011 0b0011
0b001, Normal Non-cacheable No match 0b0011 0b0011 0b0011 0b0011
0b010, Normal Cacheable RA Write-Through Match 0b0011 0b0011 0b1110 0b0110
0b010, Normal Cacheable RA Write-Through No match 0b0011 0b0011 0b1110 0b0110
0b011, Normal Cacheable RA Write-Back Match 0b1111 0b0111 0b1111 0b0111
0b011, Normal Cacheable RA Write-Back No match 0b0011 0b0011 0b1111 0b0111
0b100, Normal Cacheable WA Write-Through Match 0b0011 0b0011 0b1010 0b1110
0b100, Normal Cacheable WA Write-Through No match 0b0011 0b0011 0b1010 0b1110
0b101, Normal Cacheable WA Write-Back Match 0b1011 0b1111 0b1011 0b1111
0b101, Normal Cacheable WA Write-Back No match 0b0011 0b0011 0b1011 0b1111
0b110, Normal Cacheable WA RA Write-Through Match 0b0011 0b0011 0b1110 0b1110
0b110, Normal Cacheable WA RA Write-Through No match 0b0011 0b0011 0b1110 0b1110
0b111, Normal Cacheable WA RA Write-Back Match 0b1111 0b1111 0b1111 0b1111
0b111, Normal Cacheable WA RA Write-Back No match 0b0011 0b0011 0b1111 0b1111

Signal a<x>domain is driven according to the *BASER*.Shareability field unless the resultant cacheability is Device, or Non-cacheable, in which case it becomes 0b11, system Shareable in accordance with the Arm®AMBA® AXI and ACE Protocol Specification.

a The mappings are designed for the ARMv8 and ARMv8.2 generation of cores. However, setting this bit converts the GIC-600 to full featured mapping.
Non-ConfidentialPDF file icon PDF version100336_0104_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved. 
Home > Operation > Memory access and attributes