A.2 Power control signals

The following table shows the GIC-600 power control signals.

Table A-2 Power control signals

Signal name Type Source or destination Description
cpu_active[_<ppi_block>][_<bus>][<num_cpus − 1:0>] Input Power controller Indicates if the core is active and not in a low-power state such as retention. This is used for lowering the priority of selection for 1 of N SPIs. There is 1 bit per core on the ICC bus.
wake_request[<num_cpus − 1:0>] Output Power controller Wake request signal to power controller indicating that an interrupt is targeting this core and it must be woken. When asserted, the wake_request is sticky unless the Distributor is put into the gated state.
qreqn_col Input Low-Power Interface

Low-Power Interface to flush out the path between the SPI Collator and the Distributor to aid in power down.

When asserted, messages are not sent to the Distributor until low-power state is exited.


It is only safe to stop the Collator clock if all interrupts are level sensitive, or if edge-triggered, pulse extended into the SPI Collator.
qacceptn_col Output
qdeny_col Output
qactive_col Output
qreqn_its[<its>] Input Low-Power Interfacea

Required to flush out the path between the ITS and the Distributor.

There is one Q-Channel for each ITS.

All Distributor ITS Q-Channels are combined as a single set of vectored signals, qreqn_its[num_ITS − 1:0].

qacceptn_its[<its>] Output
qdeny_its[<its>] Output
qactive_its[<its>] Output
[<domain_>]clkqreqn Input Clock controller

Low-Power Interface for clock gating of everything in the domain.

[<domain_>]clkqreqn is synchronized into the GIC-600.

This bus must be treated asynchronously.

[<domain_>]clkqacceptn Output
[<domain_>]clkqdeny Output
[<domain_>]clkqactive Output
[<domain_>]pwrqreqn Input Power controller

ADB power interface within the domain.

See the Arm®CoreLink™ ADB-400 AMBA® Domain Bridge User Guide.

[<domain_>]pwrqacceptn Output
[<domain_>]pwrqdeny Output
[<domain_>]pwrqactive Output
preq Input Power controller

This P-Channel interface is only present in multichip configurations.

See 3.17.5 Power control and P-Channel.

preq is synchronized into the GIC-600.

pstate must be stable when preq is asserted.

This bus must be treated asynchronously.

pstate[4:0] Input
paccept Output
pdeny Output
pactive Output
a These signals are not present in monolithic configurations where the Distributor and ITS share ACE-Lite ports.
Non-ConfidentialPDF file icon PDF version100336_0104_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.