4.9.7 Interrupt Contribution Enable Set Register 0, GICP_INTENSET0

This register contains the set mechanism for the counter interrupt contribution enables. The GIC-600 supports five counters, n = 0-4.

The GICP_INTENSET0 characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee 4.9 GICP register summary.

The following figure shows the bit assignments.

Figure 4-49 GICP_INTENSET0 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the bit assignments.

Table 4-65 GICP_INTENSET0 bit assignments

Bits Name Function
[31:5] - Reserved, RAZ
[4:0] INTEN

Interrupt enable. The INTEN[n] bit is the interrupt enable for counter n. This field resets to an unknown value.

Writing 1 to a bit location sets the interrupt enable for the associated counter.

Writing 0 to a bit location has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register.

Reads return the state of the interrupt enables.

The interrupt enable for counter n is enabled when INTEN[n] == 1 and GICP_CR.E == 1.

Overflow of counter n sets GICP_OVSSET0.OVS[n] to 1 and that triggers the PMU interrupt if INTEN[n] == 1.

Non-ConfidentialPDF file icon PDF version100336_0104_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.