4.2.9 Interrupt Class Registers, GICD_ICLARn

These registers control whether a 1 of N SPI can target a core that is assigned to class 0 or class 1 group. Each register controls 16 SPIs and the GIC-600 has 60 registers, GICD_ICLAR2-GICD_ICLAR61.

The GICD_ICLARn characteristics are:

Usage constraintsThe Distributor provides up to 60 registers to support 960 SPIs. If you configure the GIC-600 to use fewer than 960 SPIs, then it reduces the number of registers accordingly. For locations where interrupts are not implemented, the register is RAZ/WI.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee 4.2 Distributor registers (GICD/GICDA) summary.

The following figure shows the bit assignments.

Figure 4-9 GICD_ICLARn bit assignments
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The following table shows the bit assignments.

Table 4-12 GICD_ICLARn bit assignments

Bits Name Function
[31,29,27,25,23,21,19,17,15,13,11,9,7,5,3,1] Class1

Controls whether the 1 of N SPI can target a core that is assigned to class 1:

0 = The SPI can target a core that is assigned to class 1 group.

1 = The SPI cannot target a core that is assigned to class 1 group.

Note:

The SPI that a bit refers to depends on its bit position and the base address offset of the GICD_ICLARn.
[30,28,26,24,22,20,18,16,14,12,10,8,6,4,2,0] Class0

Controls whether the 1 of N SPI can target a core that is assigned to class 0:

0 = The SPI can target a core that is assigned to class 0 group.

1 = The SPI cannot target a core that is assigned to class 0 group.

Note:

The SPI that a bit refers to depends on its bit position and the base address offset of the GICD_ICLARn.
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