4.8 GICT register summary

The GIC-600 trace and debug functions are controlled through registers that are identified with the prefix GICT.

Note:

The GICD_SAC.GICTNS bit controls whether Non-secure software can access the GICT registers.

Table 4-44 GICT register summary

Offset Name Type Width Reset Description RAS ?
0x0000 + (n × 64) GICT_ERR<n>FR RO 64 Record dependent 4.8.1 Error Record Feature Register, GICT_ERR<n>FR Yes
0x0008 + (n × 64) GICT_ERR<n>CTLR RW 64 0x0 4.8.2 Error Record Control Register, GICT_ERR<n>CTLR Yes
0x0010 + (n × 64) GICT_ERR<n>STATUS RW 64 Record dependent 4.8.3 Error Record Primary Status Register, GICT_ERR<n>STATUS Yes
0x0018 + (n × 64) GICT_ERR<n>ADDR RW 64 Unknown 4.8.4 Error Record Address Register, GICT_ERR<n>ADDR Yes
0x0020 + (n × 64) GICT_ERR<n>MISC0 RW 64 Unknown 4.8.5 Error Record Miscellaneous Register 0, GICT_ERR<n>MISC0 Yes
0x0028 + (n × 64) GICT_ERR<n>MISC1 RW 64 Unknown 4.8.6 Error Record Miscellaneous Register 1, GICT_ERR<n>MISC1 Yes
0xE000 GICT_ERRGSR RO 64 0x0 4.8.7 Error Group Status Register, GICT_ERRGSR Yes
0xE008-0xE7FC - - - - Reserved, RAZ/WI -
0xE800-0xE808 GICT_ERRIRQCR<n> RW 64 0x0 4.8.8 Error Interrupt Configuration Registers, GICT_ERRIRQCR<n> Yes
0xE810-0xFFB8 - - - - Reserved, RAZ/WI -
0xFFBC GICT_DEVARCH RO 32 0x47700A00 Device Architecture register Yes
0xFFC0-0xFFC4 - - - - Reserved, RAZ/WI -
0xFFC8 GICT_ERRIDR RO 32 Configuration dependent 4.8.9 Error Record ID Register, GICT_ERRIDR Yes
0xFFCC - - - - Reserved, RAZ/WI -
0xFFD0 GICT_PIDR4 RO 32 0x44 Peripheral ID 4 Register No
0xFFD4 GICT_PIDR5 RO 32 0x00 Peripheral ID 5 Register No
0xFFD8 GICT_PIDR6 RO 32 0x00 Peripheral ID 6 Register No
0xFFDC GICT_PIDR7 RO 32 0x00 Peripheral ID 7 Register No
0xFFE0 GICT_PIDR0 RO 32 0x95 Peripheral ID 0 Register No
0xFFE4 GICT_PIDR1 RO 32 0xB4 Peripheral ID 1 Register No
0xFFE8 GICT_PIDR2 RO 32 0x3B 4.8.10 Peripheral ID2 Register, GICT_PIDR2 No
0xFFEC GICT_PIDR3 RO 32 0x00 Peripheral ID 3 Register No
0xFFF0 GICT_CIDR0 RO 32 0x0D Component ID 0 Register No
0xFFF4 GICT_CIDR1 RO 32 0xF0 Component ID 1 Register No
0xFFF8 GICT_CIDR2 RO 32 0x05 Component ID 2 Register No
0xFFFC GICT_CIDR3 RO 32 0xB1 Component ID 3 Register No

The following table lists the error records for the various error conditions.

Table 4-45 Error records

Record Description Type Syndrome (SERR)
0 Software error in GICD programming UEOa See Table   3-8 Software errors, record 0.
1 Correctable SPI RAM errors CEb

7, Data value from associative memory.

See Table   3-9 SPI RAM errors, records 1-2.

2 Uncorrectable SPI RAM errors UERc

7, Data value from associative memory.

See Table   3-9 SPI RAM errors, records 1-2.

3 Correctable SGI RAM errors CEb

7, Control value from associative memory.

See Table   3-10 SGI RAM errors, records 3-4.

4 Uncorrectable SGI RAM errors UERc

7, Control value from associative memory.

See Table   3-10 SGI RAM errors, records 3-4.

5 Reserved - -
6 Reserved - -
7 Correctable PPI RAM errors CEb

7, Control value from associative memory.

See Table   3-11 PPI RAM errors, records 7-8.

8 Uncorrectable PPI RAM errors UERc

7, Control value from associative memory.

See Table   3-11 PPI RAM errors, records 7-8.

9 Correctable LPI RAM errors CEb

7, Control value from associative memory.

See Table   3-12 LPI RAM errors, records 9-10.

10 Uncorrectable LPI RAM errors UERc

7, Control value from associative memory.

See Table   3-12 LPI RAM errors, records 9-10.

11 Correctable error from ITS RAM CEb

6, Data value from associative memory.

See Table   3-13 ITS RAM errors, records 11-12.

12 Uncorrectable error from ITS RAM UEOa

6, Data value from associative memory.

See Table   3-13 ITS RAM errors, records 11-12.

13 + ITSnum ITS command and translation errors UERc

14, Illegal Access.

See Table   3-15 ITS command and translation errors, records 13+.

This section contains the following subsections:
a Restartable error and contained.
b Correctable error.
c Recoverable error.
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