4.8.2 Error Record Control Register, GICT_ERR<n>CTLR

This register controls how interrupts are handled.

The GICT_ERR<n>CTLR characteristics are:

Usage constraintsIf GICD_SAC.GICTNS == 0, then only Secure software can access the functions of this register.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee 4.8 GICT register summary.

The following figure shows the bit assignments.

Figure 4-35 GICT_ERR<n>CTLR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the bit assignments.

Table 4-47 GICT_ERR<n>CTLR bit assignments

Bits Name Function
[63:16] - Reserved, RAZ.
[15] RP 0 = An error response to a transaction is reported.
[14:9] - Reserved, RAZ.
[8] CFI

Controls whether a corrected error generates a fault handling interrupt.

SBZ on non-correctable errors else:

0 = The GIC-600 does not assert a fault handling interrupt for corrected errors.

1 = The GIC-600 asserts a fault handling interrupt when a corrected error occurs.

[7:5] -

Reserved, RAZ.

[4] UE

Uncorrected error.

RAZ/WI for all records except GICT error record (0) else:

0 = Do not send external abort with transaction.

1 = Send external abort with transaction.

[3] FI

Fault handling interrupt.

SBZ on Correctable Error (CE) records else:

0 = Fault handling interrupt is not generated on any error.

1 = Fault handling interrupt is generated on all uncorrectable errors.

[2] UI

Error recovery interrupt for uncorrected error.

SBZ on CE records else:

0 = Error recovery interrupt is not generated on any error.

1 = Error recovery interrupt is generated on all uncorrectable errors.

[1:0] - Reserved, RAZ.
Non-ConfidentialPDF file icon PDF version100336_0104_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.