4.8.5 Error Record Miscellaneous Register 0, GICT_ERR<n>MISC0

This register contains the Corrected error counter and information that assists with identifying the RAM in which the error was detected.

The GICT_ERR<n>MISC0 characteristics are:

Usage constraintsIf GICD_SAC.GICTNS == 0, then only Secure software can access the functions of this register.

If GICT_ERR<n>STATUS.MV == 1, then the GICT_ERR<n>MISC0 ignores writes to the Data field.

ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee 4.8 GICT register summary.

The following figure shows the bit assignments.

Figure 4-38 GICT_ERR<n>MISC0 bit assignments
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The following table shows the bit assignments.

Table 4-50 GICT_ERR<n>MISC0 bit assignments

Bits Name Function
[63:42] - Reserved, RAZ.
[41] RE

Rounding Error.

The Rounding Error counter is under-reporting.

[40] Overflow

Sticky overflow bit:

0 = Counter has not overflowed.

1 = Counter has overflowed.

If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt.

[39:32] Count

Corrected error count.

Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome.

[31:0] Data Information associated with the error. A description of each error code is given in one of the following tables:

The following table shows the Data field encoding for each error record and syndrome.

Table 4-51 Data field encoding

Record GICT_ERR<n>STATUS.IERR (syndrome) GICT_ERR<n>STATUS.SERR

Value and description of GICT_ERR<n>MISC0.Data (Other bits RES0)

Always packed from 0 (lowest = 0)

Software Error (0)

0x0, SYN_ACE_BAD

Illegal ACE-Lite Slave Access.

0xE

AccessRnW, bit[12].

AccessSparse, bit[11].

AccessSize, bits[10:8].

AccessLength, bits[7:0].

Software Error (0)

0x1, SYN_PPI_PWRDWN

Attempt to access a powered down Redistributor.

0xF

Redistributor, bits[24:16].

Core, bits[8:0].

Software Error (0)

0x2, SYN_PPI_PWRCHANGE

Attempt to power down Redistributor rejected.

0xF

Redistributor, bits[24:16].

Core, bits[8:0].

Software Error (0)

0x3, SYN_GICR_ARE

Attempt to access GICR or GICD registers in mode that cannot work.

0xF Core, bits[8:0].
Software Error (0)

0x4, SYN_PROPBASE_ACC

Attempt to reprogram PROPBASE registers to a value that is not accepted because another value is already in use.

0xF Core, bits[8:0].
Software Error (0)

0x5, SYN_PENDBASE_ACC

Attempt to reprogram PENDBASE registers to a value that is not accepted because another value is already in use.

0xF Core, bits[8:0].
Software Error (0)

0x6, SYN_LPI_CLR

Attempt to reprogram ENABLE_LPI when not enabled and not asleep.

0xF Core, bits[8:0].
Software Error (0)

0x7, SYN_WAKER_CHANGE

Attempt to change GICR_WAKER abandoned due to handshake rules.

0xF Core, bits[8:0].
Software Error (0)

0x8, SYN_SLEEP_FAIL

Attempt to put GIC to sleep failed because cores are not fully asleep.

0xF Core, bits[8:0].
Software Error (0)

0x9, SYN_PGE_ON_QUIESCE

Core put to sleep before its Group enables were cleared.

0xF Core, bits[8:0].
Software Error (0)

0xA, SYN_GICD_CTLR

Attempt to update GICD_CTLR was prevented due to RWP or Group enable restrictions.

0xF Data, bits[7:0].
Software Error (0)

0x10, SYN_SGI_NO_TGT

SGI sent with no valid destinations.

0xE Core, bits[8:0].
Software Error (0) 0x11,

SYN_SGI_CORRUPTED

SGI corrupted without effect.

0x6 Core, bits[8:0].
Software Error (0) 0x12,

SYN_GICR_CORRUPTED

Data was read from GICR register space that encountered an uncorrectable error.

0x6 GICT_ERR0ADDR is populated.
Software Error (0) 0x13,

SYN_GICD_CORRUPTED

Data was read from GICD register space that encountered an uncorrectable error.

0x6 GICT_ERR0ADDR is populated.
Software Error (0) 0x14,

SYN_ITS_OFF

Data was read from an ITS that is powered down.

0xF GICT_ERR0ADDR is populated.
Software Error (0)

0x18, SYN_SPI_BLOCK.

Attempt to access a SPI block that is not implemented.

0xE Block, bits[4:0].
Software Error (0)

0x19, SYN_SPI_OOR

Attempt to access a non-implemented SPI using (SET|CLR)SPI.

0xE ID, bits[9:0].
Software Error (0)

0x1A, SYN_SPI_NO_DEST_TGT

A SPI has no legal target destinations.

0xF ID, bits[9:0].
Software Error (0)

0x1B, SYN_SPI_NO_DEST_1OFN

A 1 of N SPI cannot be delivered due to bad DPG/GICR_CLASS programming.

0xF ID, bits[9:0].
Software Error (0)

0x1C, SYN_COL_OOR

A collator message is received for a non-implemented SPI, or is larger than the number of owned SPIs in a multichip configuration.

0xF ID, bits[9:0].
Software Error (0)

0x1D, SYN_DEACT_IN

A Deactivate to a non-existent SPI, or with incorrect groups set. Deactivates to LPI and non-existent PPI are not reported.

0xE None.
Software Error (0)

0x1E, SYN_SPI_CHIP_OFFLINE

An attempt was made to send a SPI to an offline chip.

0xF ID, bits[9:0].
Software Error (0)

0x28, SYN_ITS_REG_SET_OOR

An attempt was made to set an Out Of Range (OOR) interrupt. Only valid when GICR LPI injection registers are supported.

0xE

Core, bits[24:16].

Data, bits[15:0].

Software Error (0)

0x29, SYN_ITS_REG_CLR _OOR

An attempt was made to clear an OOR interrupt. Only valid when GICR LPI injection registers are supported.

0xE

Core, bits[24:16].

Data, bits[15:0].

Software Error (0)

0x2A, SYN_ITS_REG_INV_OOR

An attempt was made to invalidate an OOR interrupt. Only valid when GICR LPI injection registers are supported.

0xE

Core, bits[24:16].

Data, bits[15:0].

Software Error (0)

0x2B, SYN_ITS_REG_SET_ENB

An attempt was made to set an interrupt when LPIs are not enabled. Only valid when GICR LPI injection registers are supported.

0xF

Core, bits[24:16].

Data, bits[15:0].

Software Error (0)

0x2C, SYN_ITS_REG_CLR _ENB

An attempt was made to clear an interrupt when LPIs are not enabled. Only valid when GICR LPI injection registers are supported.

0xF

Core, bits[24:16].

Data, bits[15:0].

Software Error (0)

0x2D, SYN_ITS_REG_INV_ENB

An attempt was made to invalidate an interrupt when LPIs are not enabled. Only valid when GICR LPI injection registers are supported.

0xF

Core, bits[24:16].

Data, bits[15:0].

Software Error (0)

0x40, SYN_LPI_PROP_READ_FAIL

An attempt was made to read properties for a single interrupt where an error response was received with the data.

0x12

Target, bits[31:16].

ID, bits[15:0].

Software Error (0)

0x41, SYN_PT_PROP_READ_FAIL

An attempt was made to read properties for a block of interrupts where an error response was received with the data.

0x12

Target, bits[31:16].

ID, bits[15:0].

Software Error (0)

0x42, SYN_PT_COARSE_MAP_READ_FAIL

An attempt was made to read the coarse map for a target where an error response was received with the data.

0x12 Target, bits[31:16].
Software Error (0)

0x43, SYN_PT_COARSE_MAP_WRITE_FAIL

An attempt was made to write the coarse map for a target with an error received with the write response.

0x12 Target, bits[31:16].
Software Error (0)

0x44, SYN_PT_TABLE_READ_FAIL

An attempt was made to read a block of interrupts from a Pending table, where an error response was received with the data.

0x12

Target, bits[31:16].

ID, bits[15:0].

Software Error (0)

0x45, SYN_PT_TABLE_WRITE_FAIL

An attempt was made to write-back a block of interrupts from a Pending table with an error received with the write response.

0x12

Target, bits[31:16].

ID, bits[15:0].

Software Error (0)

0x46, SYN_PT_SUB_TABLE_READ_FAIL

An attempt was made to read a sub-block of interrupts from a Pending table, where an error response was received with the data.

0x12

Target, bits[31:16].

ID, bits[15:0].

Software Error (0)

0x47, SYN_PT_TABLE_WRITE_FAIL_BYTE

An attempt was made to write-back a subblock of interrupts from a Pending table, with an error received with the write response.

0x12

Target, bits[31:16].

ID, bits[15:0].

Correctable SPI RAM errors (1) 0x0 0x7 Bit location, ID, bits[log2(SPIs)+].
Uncorrectable SPI RAM errors (2) 0x0 0x7 ID, bits[log2(SPIs) − 1:0].
Correctable SGI RAM errors (3) 0x0 0x7

Bit location, log2(width).

Address, bits[(ceiling(cores / 16) × 16) − 1:0].

Uncorrectable SGI RAM errors (4) 0x0 0x7 Address, bits[(ceiling(cores / 16) × 16) − 1:0].
Reserved (5) - - -
Reserved (6) - - -
Correctable PPI RAM errors (7) 0x0 0x7

PPI block, bits[18+].

Bit location, bits[17:12].

Offset, bits[11:8].

SGI/Int, bit[7].

Core, bits[6:0].

Uncorrectable PPI RAM errors (8) 0x0 0x7

PPI block, bits[12+].

Offset, bits[11:8].

SGI/Int, bit[7].

Core, bits[6:0].

Correctable LPI RAM errors (9) 0x0 0x7

Bit location, bit[15+].

Reserved, bit[14].

Pendinga, bits[13:12].

Reserved, bits[11:10].

Address, bits[9:0].

Uncorrectable LPI RAM errors (10) 0x0 0x7

Pending, bits[13:12]

Reserved, bits[11:10]

Address, bits[9:0]

The corresponding data is stored in GICT_ERR<n>MISC1.

Correctable error from ITS RAM (11) 0x0 0x6

Bit location, bits[(x + 15)+].

Address, bits[(x + 14)+].

RAM, bits[x + 2:x].

ITS, bits[x − 1:0].

x = log2(ITS).

Uncorrectable error from ITS RAM (12) 0x0 0x6

Address, bits[(x + 3)+].

RAM, bits[x + 2:x].

ITS, bits[x − 1:0].

x = log2(ITS).

Command or translation error in ITS (13+)

0x0, Architectural

0x1, Non Architectural

0x1 ITS 24-bit syndrome
a Pending bits[13:12] indicate if there were pending interrupts in the cache at the time of the corruption.
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